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kab0xd100m - txgp revision 1.11 august 2003 - 1 - mcp memory sec only document title multi-chip package memory 64m bit (8mx8/4mx16) dual bank nor flash / 128m bit (8mx16) nand flash / 32m bit (2mx16) utram revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 1.0 1.1 1.11 remark preliminary preliminary preliminary final final final final history initial draft inserted no ecc condition in nand flash endurance (1page) : 1,000 program/erase cycles maximum without ecc program flow (39page) : excluded "read verify" step after programming in this condition revised t bias (43page) from "-25 to 85" to "-40 to 125" revised v il (43page) from max. 0.6v to max. 0.5v revised v oh (43page) from min. 2.4v to min. 2.3v revised iol(43page) from 0.1ma to max. 2.1ma revised ioh(43page) from -0.1ma to max. -1.0ma revised the internal voltage that disables all functions(37page) from 2v to 1.3v revised power-up and power-down recovery time(37page) from min. 1 m s to min. 10 m s revised write cycle time(twc)(59page) from 50ns to min. 45ns combined ale to re delay in id read and in read cycle(59page) from min. 20ns and 50ns to min. 10ns revised re access time(t rea )(59page) from max. 35ns to max. 30ns excluded min. value of re high to output hi-z(t reh )(59page) inserted re or ce f high to output hold(t oh ) with min. 15ns(59page) revised timing diagram finalize revised - release the stand-by current from typ. 5ua(max. 18ua) to typ. 10ua(max. 30ua). revised - corrected some typos in the timing diagram draft date march 20, 2002 march 28, 2002 march 28, 2002 june 17, 2002 october 15, 2002 june 18, 2003 august 14, 2003 note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
kab0xd100m - txgp revision 1.11 august 2003 - 2 - mcp memory sec only multi-chip package memory 64m bit (8mx8/4mx16) dual bank nor flash / 128m bit (8mx16) nand flash / 32m bit (2mx16) utram the kab0xd100m featuring single 3.0v power supply is a multi chip package memory which combines 64mbit nor flash, 128mbit nand flash and 32mbit unit transistor cmos ram. 64mbit nor flash memory is organized as 8m x8 or 4m x16 bit, 128mbit nand flash memory is organized as 8m x16 bit and 32mbit u t ram is organized as 2m x16 bit. the memory architec- ture of nor flash memory is designed to divide its memory arrays into 135 blocks and this provides highly flexible erase and program capability. this device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization. nor flash memory performs a program operation in units of 8 bits (byte) or 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed for typically 0.7sec. in 128mbit nand flash a 256-word page program can be typically achieved within 200 m s and an 8k-word block erase can be typi- cally achieved within 2ms. in serial read operation, a byte can be read by 50ns. dq pins serve as the ports for address and data input/output as well as command inputs. the kab0xd100m is suitable for the memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 80-ball tbga package. features power supply voltage : 2.7v~3.1v organization - nor flash : 8,388,608 x 8 bit / 4,194,304 x 16 bit - nand flash : (8m + 256k)bit x 16bit - u t ram : 2mbit x 16 bit access time - nor flash : 70ns(max.) - nand flash : random : 10us(max.), serial : 50ns(min.) - u t ram : 85ns power consumption (typical value) - nor flash read current : 14ma (@5mhz) program/erase current : 15ma read while program or read while erase : 35ma standby mode/autosleep mode : 10 m a - nand flash read current : 10ma(@20mhz) program/erase current : 10ma standby current : 10 m a - u t ram operating current : 30ma standby current : 80 m a nor flash secode(security code) block : extra 64kb block nor flash block group protection / unprotection nor flash bank size : 16mb / 48mb , 32mb / 32mb nand flash automatic program and erase page program: (256 + 8)word, block erase: (8k + 256)word nand flash fast write cycle time program time : 200 m s(typ.) block erase time : 2ms(typ.) endurance nor : 100,000 program/erase cycles minimum nand : 100,000 program/erase cycles minimum with ecc : 1,000 program/erase cycles maximum without ecc data retention : 10 years operating temperature : -25 c ~ 85 c package : 80 - ball tbga type - 8 x 12mm, 0.8 mm pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. ball name description a0 to a20 address input balls (nor, u t ram) a-1, a21 address input balls (nor) dq0 to dq7 data input/output balls (common) dq8 to dq15 data input/output balls (common) vcc r power supply (nor) vcc f power supply (nand) vcc u power supply (u t ram) vccq u data output buffer power (u t ram) vss ground (common) we write enable (common) oe output enable (nor,u t ram) ce r chip enable (nor) ce f chip enable (nand) cs u chip enable (u t ram) reset hardware reset (nor) wp /acc hardware write protection/program acceleration (nor) byte byte control (nor) r/ b r read/busy (nor) wp write protection (nand) cle command latch enable(nand) ale address latch enable(nand) r/ b f read/busy (nand) re output enable (nand) zz deep power down (u t ram) ub upper byte enable (u t ram) lb lower byte enable (u t ram) n.c no connection dnu do not use ball description ball configuration c l e n . c r / b f a 1 8 a l e v c c u n . c w e a 9 a 1 7 w p / n . c v s s a 2 0 a 1 0 a 7 1 2 3 4 5 6 a b c d e f v c c f r e s e t a 1 1 r e l b a 1 2 a 1 3 a 1 4 a 1 5 7 8 h g a 3 d n u d n u a 6 k j 80 ball tbga , 0.8mm pitch top view (ball down) l n m d n u d n u r / b r a 5 a 4 u b a 1 9 w p n . c a 8 c s u c e r n . c c e f n . c b y t e d q 2 d q 1 1 v c c q u v s s d q 1 2 d q 5 d q 3 z z a 2 1 d q 1 3 d q 9 n . c n . c a 1 6 d q 1 4 d q 7 d q 8 a 1 a 2 a 0 o e v c c u n . c d q 1 0 d q 6 d q 1 v c c r d q 1 5 d q 0 v c c f d q 4 d n u d n u d n u d n u a c c / a - 1
kab0xd100m - txgp revision 1.11 august 2003 - 3 - mcp memory sec only ordering information k a b 0x d 1 0 0 m - t lgp samsung mcp memory (3chip mcp) device type b : dual bank nor + nand + u t ram nor flash density, vcc, & org. : 64m, vcc=3.0v, & org.=x8/x16 : bank size(boot block) 01 : 16m/48m(bottom), 02 : 16m/48m(top) 03 : 32m/32m(bottom), 04 : 32m/32m(top) sram density (vcc, org.) 0 : none dram i/f, density (vcc, org.) 0 : none u t ram density (vcc, org.) 1 : 32m (3.0v, x16) package t = 80 tbga nand flash density (vcc, org.) d : 128m (3.0v, x16) figure 1. functional block diagram a0 to a20 ce r oe cle ce f vss we vcc r vss i/o interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank2 cell array bank1 address bank2 address bank1 data-in/out bank2 data-in/out bank1 cell array wp byte ale reset vcc f x-buffers y-gating 128m+4m bit command 2nd half page register & s/a nand flash array (256 + 8)word x 32768 y-gating 1st half page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver bottom boot block precharge circuit. i/o circuit column select clk gen. row select data control control logic u t ram (2mb x16) main cell array ub vcc u vss cs u lb zz r/ b r a-1, a21 vccq u r/ b f re version m = 1st generation access time lgp : nor(70ns) nand(50ns), u t ram(85ns) ngp : nor(80ns) nand(50ns), u t ram(85ns) dq 0 to dq 15 dq 0 to dq 15 dq 0 to dq 15 dq 0 to dq 15
kab0xd100m - txgp revision 1.11 august 2003 - 4 - mcp memory sec only 256 words 8 words page register (=256 bytes) 32k pages (=1024 blocks) 256 words 16 bit 8 words 1 block =32 pages = (8k + 256) words dq 0 ~ dq 15 1 page = 264 words 1 block = 264 words x 32 pages = (8k + 256) words 1 device = 264 words x 32pages x 1024blocks = 132 mbits page register figure 2. nand flash array organization note: column address : starting address of the register. * l must be set to "low" dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq8 to 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 *l 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 *l 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 *l *l column address row address (page address)
kab0xd100m - txgp revision 1.11 august 2003 - 5 - mcp memory sec only table 1. nor flash memory top boot block address (kab02d100/kab04d100) kab 02d1 00 kab 04d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank1 bank1 ba134 1 1 1 1 1 1 1 1 1 1 8/4 7fe000h-7fffffh 3ff000h-3fffffh ba133 1 1 1 1 1 1 1 1 1 0 8/4 7fc000h-7fdfffh 3fe000h-3fefffh ba132 1 1 1 1 1 1 1 1 0 1 8/4 7fa000h-7fbfffh 3fd000h-3fdfffh ba131 1 1 1 1 1 1 1 1 0 0 8/4 7f8000h-7f9fffh 3fc000h-3fcfffh ba130 1 1 1 1 1 1 1 0 1 1 8/4 7f6000h-7f7fffh 3fb000h-3fbfffh ba129 1 1 1 1 1 1 1 0 1 0 8/4 7f4000h-7f5fffh 3fa000h-3fafffh ba128 1 1 1 1 1 1 1 0 0 1 8/4 7f2000h-7f3fffh 3f9000h-3f9fffh ba127 1 1 1 1 1 1 1 0 0 0 8/4 7f0000h-7f1fffh 3f8000h-3f8fffh ba126 1 1 1 1 1 1 0 x x x 64/32 7e0000h-7effffh 3f0000h-3f7fffh ba125 1 1 1 1 1 0 1 x x x 64/32 7d0000h-7dffffh 3e8000h-3effffh ba124 1 1 1 1 1 0 0 x x x 64/32 7c0000h-7cffffh 3e0000h-3e7fffh ba123 1 1 1 1 0 1 1 x x x 64/32 7b0000h-7bffffh 3d8000h-3dffffh ba122 1 1 1 1 0 1 0 x x x 64/32 7a0000h-7affffh 3d0000h-3d7fffh ba121 1 1 1 1 0 0 1 x x x 64/32 790000h-79ffffh 3c8000h-3cffffh ba120 1 1 1 1 0 0 0 x x x 64/32 780000h-78ffffh 3c0000h-3c7fffh ba119 1 1 1 0 1 1 1 x x x 64/32 770000h-77ffffh 3b8000h-3bffffh ba118 1 1 1 0 1 1 0 x x x 64/32 760000h-76ffffh 3b0000h-3b7fffh ba117 1 1 1 0 1 0 1 x x x 64/32 750000h-75ffffh 3a8000h-3affffh ba116 1 1 1 0 1 0 0 x x x 64/32 740000h-74ffffh 3a0000h-3a7fffh ba115 1 1 1 0 0 1 1 x x x 64/32 730000h-73ffffh 398000h-39ffffh ba114 1 1 1 0 0 1 0 x x x 64/32 720000h-72ffffh 390000h-397fffh ba113 1 1 1 0 0 0 1 x x x 64/32 710000h-71ffffh 388000h-38ffffh ba112 1 1 1 0 0 0 0 x x x 64/32 700000h-70ffffh 380000h-387fffh ba111 1 1 0 1 1 1 1 x x x 64/32 6f0000h-6fffffh 378000h-37ffffh ba110 1 1 0 1 1 1 0 x x x 64/32 6e0000h-6effffh 370000h-377fffh ba109 1 1 0 1 1 0 1 x x x 64/32 6d0000h-6dffffh 368000h-36ffffh ba108 1 1 0 1 1 0 0 x x x 64/32 6c0000h-6cffffh 360000h-367fffh ba107 1 1 0 1 0 1 1 x x x 64/32 6b0000h-6bffffh 358000h-35ffffh ba106 1 1 0 1 0 1 0 x x x 64/32 6a0000h-6affffh 350000h-357fffh ba105 1 1 0 1 0 0 1 x x x 64/32 690000h-69ffffh 348000h-34ffffh ba104 1 1 0 1 0 0 0 x x x 64/32 680000h-68ffffh 340000h-347fffh ba103 1 1 0 0 1 1 1 x x x 64/32 670000h-67ffffh 338000h-33ffffh ba102 1 1 0 0 1 1 0 x x x 64/32 660000h-66ffffh 330000h-337fffh ba101 1 1 0 0 1 0 1 x x x 64/32 650000h-65ffffh 328000h-32ffffh ba100 1 1 0 0 1 0 0 x x x 64/32 640000h-64ffffh 320000h-327fffh ba99 1 1 0 0 0 1 1 x x x 64/32 630000h-63ffffh 318000h-31ffffh
kab0xd100m - txgp revision 1.11 august 2003 - 6 - mcp memory sec only table 1. nor flash memory top boot block address (kab02d100/kab04d100) kab 02d1 00 kab 04d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank1 bank1 ba98 1 1 0 0 0 1 0 x x x 64/32 620000h-62ffffh 310000h-317fffh ba97 1 1 0 0 0 0 1 x x x 64/32 610000h-61ffffh 308000h-30ffffh ba96 1 1 0 0 0 0 0 x x x 64/32 600000h-60ffffh 300000h-307fffh bank2 ba95 1 0 1 1 1 1 1 x x x 64/32 5f0000h-5fffffh 2f8000h-2fffffh ba94 1 0 1 1 1 1 0 x x x 64/32 5e0000h-5effffh 2f0000h-2f7fffh ba93 1 0 1 1 1 0 1 x x x 64/32 5d0000h-5dffffh 2e8000h-2effffh ba92 1 0 1 1 1 0 0 x x x 64/32 5c0000h-5cffffh 2e0000h-2e7fffh ba91 1 0 1 1 0 1 1 x x x 64/32 5b0000h-5bffffh 2d8000h-2dffffh ba90 1 0 1 1 0 1 0 x x x 64/32 5a0000h-5affffh 2d0000h-2d7fffh ba89 1 0 1 1 0 0 1 x x x 64/32 590000h-59ffffh 2c8000h20cffffh ba88 1 0 1 1 0 0 0 x x x 64/32 580000h-58ffffh 2c0000h-2c7fffh ba87 1 0 1 0 1 1 1 x x x 64/32 570000h-57ffffh 2b8000h-2bffffh ba86 1 0 1 0 1 1 0 x x x 64/32 560000h-56ffffh 2b0000h-2b7fffh ba85 1 0 1 0 1 0 1 x x x 64/32 550000h-55ffffh 2a8000h-2affffh ba84 1 0 1 0 1 0 0 x x x 64/32 540000h-54ffffh 2a0000h-2a7fffh ba83 1 0 1 0 0 1 1 x x x 64/32 530000h-53ffffh 298000h-29ffffh ba82 1 0 1 0 0 1 0 x x x 64/32 520000h-52ffffh 290000h-297fffh ba81 1 0 1 0 0 0 1 x x x 64/32 510000h-51ffffh 288000h-28ffffh ba80 1 0 1 0 0 0 0 x x x 64/32 500000h-50ffffh 280000h-287fffh ba79 1 0 0 1 1 1 1 x x x 64/32 4f0000h-4fffffh 278000h-27ffffh ba78 1 0 0 1 1 1 0 x x x 64/32 4e0000h-4effffh 270000h-277fffh ba77 1 0 0 1 1 0 1 x x x 64/32 4d0000h-4dffffh 268000h-26ffffh ba76 1 0 0 1 1 0 0 x x x 64/32 4c0000h-4cffffh 260000h-267fffh ba75 1 0 0 1 0 1 1 x x x 64/32 4b0000h-4bffffh 258000h-25ffffh ba74 1 0 0 1 0 1 0 x x x 64/32 4a0000h-4affffh 250000h-257fffh ba73 1 0 0 1 0 0 1 x x x 64/32 490000h-49ffffh 248000h-24ffffh ba72 1 0 0 1 0 0 0 x x x 64/32 480000h-48ffffh 240000h-247fffh ba71 1 0 0 0 1 1 1 x x x 64/32 470000h-47ffffh 238000h-23ffffh
kab0xd100m - txgp revision 1.11 august 2003 - 7 - mcp memory sec only table 1. nor flash memory top boot block address (kab02d100/kab04d100) kab 02d1 00 kab 04d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank1 ba70 1 0 0 0 1 1 0 x x x 64/32 460000h-46ffffh 230000h-237fffh ba69 1 0 0 0 1 0 1 x x x 64/32 450000h-45ffffh 228000h-22ffffh ba68 1 0 0 0 1 0 0 x x x 64/32 440000h-44ffffh 220000h-227fffh ba67 1 0 0 0 0 1 1 x x x 64/32 430000h-43ffffh 218000h-21ffffh ba66 1 0 0 0 0 1 0 x x x 64/32 420000h-42ffffh 210000h-217fffh ba65 1 0 0 0 0 0 1 x x x 64/32 410000h-41ffffh 208000h-20ffffh ba64 1 0 0 0 0 0 0 x x x 64/32 400000h-3fffffh 200000h-207fffh bank2 ba63 0 1 1 1 1 1 1 x x x 64/32 3f0000h-3fffffh 1f8000h-1fffffh ba62 0 1 1 1 1 1 0 x x x 64/32 3e0000h-3effffh 1f0000h-1f7fffh ba61 0 1 1 1 1 0 1 x x x 64/32 3d0000h-3dffffh 1e8000h-1effffh ba60 0 1 1 1 1 0 0 x x x 64/32 3c0000h-3cffffh 1e0000h-1e7fffh ba59 0 1 1 1 0 1 1 x x x 64/32 3b0000h-3bffffh 1d8000h-1dffffh ba58 0 1 1 1 0 1 0 x x x 64/32 3a0000h-3affffh 1d0000h-1d7fffh ba57 0 1 1 1 0 0 1 x x x 64/32 390000h-39ffffh 1c8000h-1cffffh ba56 0 1 1 1 0 0 0 x x x 64/32 380000h-38ffffh 1c0000h-1c7fffh ba55 0 1 1 0 1 1 1 x x x 64/32 370000h-37ffffh 1b8000h-1bffffh ba54 0 1 1 0 1 1 0 x x x 64/32 360000h-36ffffh 1b0000h-1b7fffh ba53 0 1 1 0 1 0 1 x x x 64/32 350000h-35ffffh 1a8000h-1affffh ba52 0 1 1 0 1 0 0 x x x 64/32 340000h-34ffffh 1a0000h-1a7fffh ba51 0 1 1 0 0 1 1 x x x 64/32 330000h-33ffffh 198000h-19ffffh ba50 0 1 1 0 0 1 0 x x x 64/32 320000h-32ffffh 190000h-197fffh ba49 0 1 1 0 0 0 1 x x x 64/32 310000h-31ffffh 188000h-18ffffh ba48 0 1 1 0 0 0 0 x x x 64/32 300000h-30ffffh 180000h-187fffh ba47 0 1 0 1 1 1 1 x x x 64/32 2f0000h-2fffffh 178000h-17ffffh ba46 0 1 0 1 1 1 0 x x x 64/32 2e0000h-2effffh 170000h-177fffh ba45 0 1 0 1 1 0 1 x x x 64/32 2d0000h-2dffffh 168000h-16ffffh ba44 0 1 0 1 1 0 0 x x x 64/32 2c0000h-2cffffh 160000h-167fffh ba43 0 1 0 1 0 1 1 x x x 64/32 2b0000h-2bffffh 158000h-15ffffh ba42 0 1 0 1 0 1 0 x x x 64/32 2a0000h-2affffh 150000h-157fffh ba41 0 1 0 1 0 0 1 x x x 64/32 290000h-29ffffh 148000h-14ffffh ba40 0 1 0 1 0 0 0 x x x 64/32 280000h-28ffffh 140000h-147fffh ba39 0 1 0 0 1 1 1 x x x 64/32 270000h-27ffffh 138000h-13ffffh ba38 0 1 0 0 1 1 0 x x x 64/32 260000h-26ffffh 130000h-137fffh ba37 0 1 0 0 1 0 1 x x x 64/32 250000h-25ffffh 128000h-12ffffh ba36 0 1 0 0 1 0 0 x x x 64/32 240000h-24ffffh 120000h-127fffh ba35 0 1 0 0 0 1 1 x x x 64/32 230000h-23ffffh 118000h-11ffffh
kab0xd100m - txgp revision 1.11 august 2003 - 8 - mcp memory sec only table 1. nor flash memory top boot block address (kab02d100/kab04d100) note: the bank address bits are a21 ~ a20 for kab02d100, a21 for kab04d100. kab 02d1 00 kab 04d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank2 ba34 0 1 0 0 0 1 0 x x x 64/32 220000h-22ffffh 110000h-117fffh ba33 0 1 0 0 0 0 1 x x x 64/32 210000h-21ffffh 108000h-10ffffh ba32 0 1 0 0 0 0 0 x x x 64/32 200000h-20ffffh 100000h-107fffh ba31 0 0 1 1 1 1 1 x x x 64/32 1f0000h-1fffffh 0f8000h-0fffffh ba30 0 0 1 1 1 1 0 x x x 64/32 1e0000h-1effffh 0f0000h-0f7fffh ba29 0 0 1 1 1 0 1 x x x 64/32 1d0000h-1dffffh 0e8000h-0effffh ba28 0 0 1 1 1 0 0 x x x 64/32 1c0000h-1cffffh 0e0000h-0e7fffh ba27 0 0 1 1 0 1 1 x x x 64/32 1b0000h-1bffffh 0d8000h-0dffffh ba26 0 0 1 1 0 1 0 x x x 64/32 1a0000h-1affffh 0d0000h-0d7fffh ba25 0 0 1 1 0 0 1 x x x 64/32 190000h-19ffffh 0c8000h-0cffffh ba24 0 0 1 1 0 0 0 x x x 64/32 180000h-18ffffh 0c0000h-0c7fffh ba23 0 0 1 0 1 1 1 x x x 64/32 170000h-17ffffh 0b8000h-0bffffh ba22 0 0 1 0 1 1 0 x x x 64/32 160000h-16ffffh 0b0000h-0b7fffh ba21 0 0 1 0 1 0 1 x x x 64/32 150000h-15ffffh 0a8000h-0affffh ba20 0 0 1 0 1 0 0 x x x 64/32 140000h-14ffffh 0a0000h-0a7fffh ba19 0 0 1 0 0 1 1 x x x 64/32 130000h-13ffffh 098000h-09ffffh ba18 0 0 1 0 0 1 0 x x x 64/32 120000h-12ffffh 090000h-097fffh ba17 0 0 1 0 0 0 1 x x x 64/32 110000h-11ffffh 088000h-08ffffh ba16 0 0 1 0 0 0 0 x x x 64/32 100000h-10ffffh 080000h-087fffh ba15 0 0 0 1 1 1 1 x x x 64/32 0f0000h-0fffffh 078000h-07ffffh ba14 0 0 0 1 1 1 0 x x x 64/32 0e0000h-0effffh 070000h-077fffh ba13 0 0 0 1 1 0 1 x x x 64/32 0d0000h-0dffffh 068000h-06ffffh ba12 0 0 0 1 1 0 0 x x x 64/32 0c0000h-0cffffh 060000h-067fffh ba11 0 0 0 1 0 1 1 x x x 64/32 0b0000h-0bffffh 058000h-05ffffh ba10 0 0 0 1 0 1 0 x x x 64/32 0a0000h-0affffh 050000h-057fffh ba9 0 0 0 1 0 0 1 x x x 64/32 090000h-09ffffh 048000h-04ffffh ba8 0 0 0 1 0 0 0 x x x 64/32 080000h-08ffffh 040000h-047fffh ba7 0 0 0 0 1 1 1 x x x 64/32 070000h-07ffffh 038000h-03ffffh ba6 0 0 0 0 1 1 0 x x x 64/32 060000h-06ffffh 030000h-037fffh ba5 0 0 0 0 1 0 1 x x x 64/32 050000h-05ffffh 028000h-02ffffh ba4 0 0 0 0 1 0 0 x x x 64/32 040000h-04ffffh 020000h-027fffh ba3 0 0 0 0 0 1 1 x x x 64/32 030000h-03ffffh 018000h-01ffffh ba2 0 0 0 0 0 1 0 x x x 64/32 020000h-02ffffh 010000h-017fffh ba1 0 0 0 0 0 0 1 x x x 64/32 010000h-01ffffh 008000h-00ffffh ba0 0 0 0 0 0 0 0 x x x 64/32 000000h-00ffffh 000000h-007fffh table 2. secode block addresses for top boot devices device block address a21-a12 block size (x8) address range (x16) address range kab02d100/kab04d100 11 11111xxx 64/32 7f0000h-7fffffh 3f8000h-3fffffh
kab0xd100m - txgp revision 1.11 august 2003 - 9 - mcp memory sec only table 3. nor flash memory bottom boot block address (kab01d100/kab03d100) kab 01d1 00 kab 03d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank2 ba134 1 1 1 1 1 1 1 x x x 64/32 7f0000h-7fffffh 3f8000h-3fffffh ba133 1 1 1 1 1 1 0 x x x 64/32 7e0000h-7effffh 3f0000h-3f7fffh ba132 1 1 1 1 1 0 1 x x x 64/32 7d0000h-7dffffh 3e8000h-3effffh ba131 1 1 1 1 1 0 0 x x x 64/32 7c0000h-7cffffh 3e0000h-3e7fffh ba130 1 1 1 1 0 1 1 x x x 64/32 7b0000h-7bffffh 3d8000h-3dffffh ba129 1 1 1 1 0 1 0 x x x 64/32 7a0000h-7affffh 3d0000h-3d7fffh ba128 1 1 1 1 0 0 1 x x x 64/32 790000h-79ffffh 3c8000h-3cffffh ba127 1 1 1 1 0 0 0 x x x 64/32 780000h-78ffffh 3c0000h-3c7fffh ba126 1 1 1 0 1 1 1 x x x 64/32 770000h-77ffffh 3b8000h-3bffffh ba125 1 1 1 0 1 1 0 x x x 64/32 760000h-76ffffh 3b0000h-3b7fffh ba124 1 1 1 0 1 0 1 x x x 64/32 750000h-75ffffh 3a8000h-3affffh ba123 1 1 1 0 1 0 0 x x x 64/32 740000h-74ffffh 3a0000h-3a7fffh ba122 1 1 1 0 0 1 1 x x x 64/32 730000h-73ffffh 398000h-39ffffh ba121 1 1 1 0 0 1 0 x x x 64/32 720000h-72ffffh 390000h-397fffh ba120 1 1 1 0 0 0 1 x x x 64/32 710000h-71ffffh 388000h-38ffffh ba119 1 1 1 0 0 0 0 x x x 64/32 700000h-70ffffh 380000h-387fffh ba118 1 1 0 1 1 1 1 x x x 64/32 6f0000h-6f1fffh 378000h-37ffffh ba117 1 1 0 1 1 1 0 x x x 64/32 6e0000h-6effffh 370000h-377fffh ba116 1 1 0 1 1 0 1 x x x 64/32 6d0000h-6dffffh 368000h-36ffffh ba115 1 1 0 1 1 0 0 x x x 64/32 6c0000h-6cffffh 360000h-367fffh ba114 1 1 0 1 0 1 1 x x x 64/32 6b0000h-6bffffh 358000h-35ffffh ba113 1 1 0 1 0 1 0 x x x 64/32 6a0000h-6affffh 350000h-357fffh ba112 1 1 0 1 0 0 1 x x x 64/32 690000h-69ffffh 348000h-34ffffh ba111 1 1 0 1 0 0 0 x x x 64/32 680000h-68ffffh 340000h-347fffh ba110 1 1 0 0 1 1 1 x x x 64/32 670000h-67ffffh 338000h-33ffffh ba109 1 1 0 0 1 1 0 x x x 64/32 660000h-66ffffh 330000h-337fffh ba108 1 1 0 0 1 0 1 x x x 64/32 650000h-65ffffh 328000h-32ffffh ba107 1 1 0 0 1 0 0 x x x 64/32 640000h-64ffffh 320000h-327fffh ba106 1 1 0 0 0 1 1 x x x 64/32 630000h-63ffffh 318000h-31ffffh ba105 1 1 0 0 0 1 0 x x x 64/32 620000h-62ffffh 310000h-317fffh ba104 1 1 0 0 0 0 1 x x x 64/32 610000h-61ffffh 308000h-30ffffh ba103 1 1 0 0 0 0 0 x x x 64/32 600000h-60ffffh 300000h-307fffh ba102 1 0 1 1 1 1 1 x x x 64/32 5f0000h-5fffffh 2f8000h-2fffffh ba101 1 0 1 1 1 1 0 x x x 64/32 5e0000h-5effffh 2f0000h-2f7fffh ba100 1 0 1 1 1 0 1 x x x 64/32 5d0000h-5dffffh 2e8000h-2effffh ba99 1 0 1 1 1 0 0 x x x 64/32 5c0000h-5cffffh 2e0000h-2e7fffh
kab0xd100m - txgp revision 1.11 august 2003 - 10 - mcp memory sec only table 3. nor flash memory bottom block address (kab01d100/kab03d100) kab 01d1 00 kab 03d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank2 ba98 1 0 1 1 0 1 1 x x x 64/32 5b0000h-5bffffh 2d8000h-2dffffh ba97 1 0 1 1 0 1 0 x x x 64/32 5a0000h-5affffh 2d0000h-2d7fffh ba96 1 0 1 1 0 0 1 x x x 64/32 590000h-59ffffh 2c8000h-2cffffh ba95 1 0 1 1 0 0 0 x x x 64/32 580000h-58ffffh 2c0000h-2c7fffh ba94 1 0 1 0 1 1 1 x x x 64/32 570000h-57ffffh 2b8000h-2bffffh ba93 1 0 1 0 1 1 0 x x x 64/32 560000h-56ffffh 2b0000h-2b7fffh ba92 1 0 1 0 1 0 1 x x x 64/32 550000h-55ffffh 2a8000h-2affffh ba91 1 0 1 0 1 0 0 x x x 64/32 540000h-54ffffh 2a0000h-2a7fffh ba90 1 0 1 0 0 1 1 x x x 64/32 530000h-53ffffh 298000h-29ffffh ba89 1 0 1 0 0 1 0 x x x 64/32 520000h-52ffffh 290000h-297fffh ba88 1 0 1 0 0 0 1 x x x 64/32 510000h-51ffffh 288000h-28ffffh ba87 1 0 1 0 0 0 0 x x x 64/32 500000h-50ffffh 280000h-287fffh ba86 1 0 0 1 1 1 1 x x x 64/32 4f0000h-4fffffh 278000h-27ffffh ba85 1 0 0 1 1 1 0 x x x 64/32 4e0000h-4effffh 270000h-277fffh ba84 1 0 0 1 1 0 1 x x x 64/32 4d0000h-4dffffh 268000h-26ffffh ba83 1 0 0 1 1 0 0 x x x 64/32 4c0000h-4cffffh 260000h-267fffh ba82 1 0 0 1 0 1 1 x x x 64/32 4b0000h-4bffffh 258000h-25ffffh ba81 1 0 0 1 0 1 0 x x x 64/32 4a0000h-4affffh 250000h-257fffh ba80 1 0 0 1 0 0 1 x x x 64/32 490000h-49ffffh 248000h-24ffffh ba79 1 0 0 1 0 0 0 x x x 64/32 480000h-48ffffh 240000h-247fffh ba78 1 0 0 0 1 1 1 x x x 64/32 470000h-47ffffh 238000h-23ffffh ba77 1 0 0 0 1 1 0 x x x 64/32 460000h-46ffffh 230000h-237fffh ba76 1 0 0 0 1 0 1 x x x 64/32 450000h-45ffffh 228000h-22ffffh ba75 1 0 0 0 1 0 0 x x x 64/32 440000h-44ffffh 220000h-227fffh ba74 1 0 0 0 0 1 1 x x x 64/32 430000h-43ffffh 218000h-21ffffh ba73 1 0 0 0 0 1 0 x x x 64/32 420000h-42ffffh 210000h-217fffh ba72 1 0 0 0 0 0 1 x x x 64/32 410000h-41ffffh 208000h-20ffffh ba71 1 0 0 0 0 0 0 x x x 64/32 400000h-40ffffh 200000h-207fffh
kab0xd100m - txgp revision 1.11 august 2003 - 11 - mcp memory sec only table 3. nor flash memory bottom boot block address (kab01d100/kab03d100) kab 01d1 00 kab 03d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank1 ba70 0 1 1 1 1 1 1 x x x 64/32 3f0000h-3fffffh 1f8000h-1f f fffh ba69 0 1 1 1 1 1 0 x x x 64/32 3e0000h-3effffh 1f0000h-1f7fffh ba68 0 1 1 1 1 0 1 x x x 64/32 3d0000h-3dffffh 1e8000h-1effffh ba67 0 1 1 1 1 0 0 x x x 64/32 3c0000h-3cffffh 1e0000h-1e7fffh ba66 0 1 1 1 0 1 1 x x x 64/32 3b0000h-3bffffh 1d8000h-1dffffh ba65 0 1 1 1 0 1 0 x x x 64/32 3a0000h-3affffh 1d0000h-1d7fffh ba64 0 1 1 1 0 0 1 x x x 64/32 390000h-39ffffh 1c8000h-1cffffh ba63 0 1 1 1 0 0 0 x x x 64/32 380000h-38ffffh 1c0000h-1c7fffh ba62 0 1 1 0 1 1 1 x x x 64/32 370000h-37ffffh 1b8000h-1bffffh ba61 0 1 1 0 1 1 0 x x x 64/32 360000h-36ffffh 1b0000h-1b7fffh ba60 0 1 1 0 1 0 1 x x x 64/32 350000h-35ffffh 1a8000h-1affffh ba59 0 1 1 0 1 0 0 x x x 64/32 340000h-34ffffh 1a0000h-1a7fffh ba58 0 1 1 0 0 1 1 x x x 64/32 330000h-33ffffh 198000h-19ffffh ba57 0 1 1 0 0 1 0 x x x 64/32 320000h-32ffffh 190000h-197fffh ba56 0 1 1 0 0 0 1 x x x 64/32 310000h-31ffffh 188000h-18ffffh ba55 0 1 1 0 0 0 0 x x x 64/32 300000h-30ffffh 180000h-187fffh ba54 0 1 0 1 1 1 1 x x x 64/32 2f0000h-2f1fffh 178000h-17ffffh ba53 0 1 0 1 1 1 0 x x x 64/32 2e0000h-2effffh 170000h-177fffh ba52 0 1 0 1 1 0 1 x x x 64/32 2d0000h-2dffffh 168000h-16ffffh ba51 0 1 0 1 1 0 0 x x x 64/32 2c0000h-2cffffh 160000h-167fffh ba50 0 1 0 1 0 1 1 x x x 64/32 2b0000h-2bffffh 158000h-15ffffh ba49 0 1 0 1 0 1 0 x x x 64/32 2a0000h-2affffh 150000h-157fffh ba48 0 1 0 1 0 0 1 x x x 64/32 290000h-29ffffh 148000h-14ffffh ba47 0 1 0 1 0 0 0 x x x 64/32 280000h-28ffffh 140000h-147fffh ba46 0 1 0 0 1 1 1 x x x 64/32 270000h-27ffffh 138000h-13ffffh ba45 0 1 0 0 1 1 0 x x x 64/32 260000h-26ffffh 130000h-137fffh ba44 0 1 0 0 1 0 1 x x x 64/32 250000h-25ffffh 128000h-12ffffh ba43 0 1 0 0 1 0 0 x x x 64/32 240000h-24ffffh 120000h-127fffh ba42 0 1 0 0 0 1 1 x x x 64/32 230000h-23ffffh 118000h-11ffffh ba41 0 1 0 0 0 1 0 x x x 64/32 220000h-22ffffh 110000h-117fffh ba40 0 1 0 0 0 0 1 x x x 64/32 210000h-21ffffh 108000h-10ffffh ba39 0 1 0 0 0 0 0 x x x 64/32 200000h-20ffffh 100000h-107fffh bank1 ba38 0 0 1 1 1 1 1 x x x 64/32 1f0000h-1fffffh 0f8000h-0fffffh ba37 0 0 1 1 1 1 0 x x x 64/32 1e0000h-1effffh 0f0000h-0f7fffh ba36 0 0 1 1 1 0 1 x x x 64/32 1d0000h-1dffffh 0e8000h-0effffh ba35 0 0 1 1 1 0 0 x x x 64/32 1c0000h-1cffffh 0e0000h-0e7fffh
kab0xd100m - txgp revision 1.11 august 2003 - 12 - mcp memory sec only table 3. nor flash memory bottom block address (kab01d100/kab03d100) note: the bank address bits are a21 ~ a20 for kab01d100, a21 for kab04d100. kab 01d1 00 kab 03d1 00 block block address block size (kb/kw) address range a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank1 bank1 ba34 0 0 1 1 0 1 1 x x x 64/32 1b0000h-1bffffh 0d8000h-0dffffh ba33 0 0 1 1 0 1 0 x x x 64/32 1a0000h-1affffh 0d0000h-0d7fffh ba32 0 0 1 1 0 0 1 x x x 64/32 190000h-19ffffh 0c8000h-0cffffh ba31 0 0 1 1 0 0 0 x x x 64/32 180000h-18ffffh 0c0000h-0c7fffh ba30 0 0 1 0 1 1 1 x x x 64/32 170000h-17ffffh 0b8000h-0bffffh ba29 0 0 1 0 1 1 0 x x x 64/32 160000h-16ffffh 0b0000h-0b7fffh ba28 0 0 1 0 1 0 1 x x x 64/32 150000h-15ffffh 0a8000h-0affffh ba27 0 0 1 0 1 0 0 x x x 64/32 140000h-14ffffh 0a0000h-0a7fffh ba26 0 0 1 0 0 1 1 x x x 64/32 130000h-13ffffh 098000h-09ffffh ba25 0 0 1 0 0 1 0 x x x 64/32 120000h-12ffffh 090000h-097fffh ba24 0 0 1 0 0 0 1 x x x 64/32 110000h-11ffffh 088000h-08ffffh ba23 0 0 1 0 0 0 0 x x x 64/32 100000h-10ffffh 080000h-087fffh ba22 0 0 0 1 1 1 1 x x x 64/32 0f0000h-0fffffh 078000h-07ffffh ba21 0 0 0 1 1 1 0 x x x 64/32 0e0000h-0effffh 070000h-077fffh ba20 0 0 0 1 1 0 1 x x x 64/32 0d0000h-0dffffh 068000h-06ffffh ba19 0 0 0 1 1 0 0 x x x 64/32 0c0000h-0cffffh 060000h-067fffh ba18 0 0 0 1 0 1 1 x x x 64/32 0b0000h-0bffffh 058000h-05ffffh ba17 0 0 0 1 0 1 0 x x x 64/32 0a0000h-0affffh 050000h-057fffh ba16 0 0 0 1 0 0 1 x x x 64/32 090000h-09ffffh 048000h-04ffffh ba15 0 0 0 1 0 0 0 x x x 64/32 080000h-08ffffh 040000h-047fffh ba14 0 0 0 0 1 1 1 x x x 64/32 070000h-07ffffh 038000h-03ffffh ba13 0 0 0 0 1 1 0 x x x 64/32 060000h-06ffffh 030000h-037fffh ba12 0 0 0 0 1 0 1 x x x 64/32 050000h-05ffffh 028000h-02ffffh ba11 0 0 0 0 1 0 0 x x x 64/32 040000h-04ffffh 020000h-027fffh ba10 0 0 0 0 0 1 1 x x x 64/32 030000h-03ffffh 018000h-01ffffh ba9 0 0 0 0 0 1 0 x x x 64/32 020000h-02ffffh 010000h-017fffh ba8 0 0 0 0 0 0 1 x x x 64/32 010000h-01ffffh 008000h-00ffffh ba7 0 0 0 0 0 0 0 1 1 1 8/4 00e000h-00ffffh 007000h-007fffh ba6 0 0 0 0 0 0 0 1 1 0 8/4 00c000h-00dfffh 006000h-006fffh ba5 0 0 0 0 0 0 0 1 0 1 8/4 00a000h-00bfffh 005000h-005fffh ba4 0 0 0 0 0 0 0 1 0 0 8/4 008000h-009fffh 004000h-004fffh ba3 0 0 0 0 0 0 0 0 1 1 8/4 006000h-007fffh 003000h-003fffh ba2 0 0 0 0 0 0 0 0 1 0 8/4 004000h-005fffh 002000h-002fffh ba1 0 0 0 0 0 0 0 0 0 1 8/4 002000h-003fffh 001000h-001fffh ba0 0 0 0 0 0 0 0 0 0 0 8/4 000000h-001fffh 000000h-000fffh table 4. secode block addresses for bottom boot devices device block address a21-a12 block size (x8) address range (x16) address range kab01d100/kab03d100 0000000xxx 64/32 000000h-00ffffh 000000h- 0 07f f fh
kab0xd100m - txgp revision 1.11 august 2003 - 13 - mcp memory sec only nor flash memory command definitions the nor flash memory operates by selecting and executing its operational modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the com- mand register. writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register command sequences are stated in table 5. note that erase suspend (b0h) and erase resume (30h) commands are valid only while the block erase operation is in progress. table 5. command sequences command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle word byte word byte word byte word byte word byte word byte read addr 1 ra data rd reset addr 1 xxxh data f0h autoselect manufacturer id (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x00h da/ x00h data aah 55h 90h ech autoselect device code (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x01h da/ x02h data aah 55h 90h (see table 9) autoselect block group protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah ba / x02h ba/ x04h data aah 55h 90h (see table 9) auto select secode block factory protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da / x03h da/ x06h data aah 55h 90h (see table 9) enter secode block region addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 88h exit secode block region addr 4 555h aaah 2aah 555h 555h aaah xxxh data aah 55h 90h 00h program addr 4 555h aaah 2aah 555h 555h aaah pa data aah 55h a0h pd unlock bypass addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass reset addr 2 xxxh xxxh data 90h 00h chip erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h 555h aaah data aah 55h 80h aah 55h 10h block erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h ba data aah 55h 80h aah 55h 30h block erase suspend (4, 5) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h cfi query (6) addr 1 55h aah data 98h
kab0xd100m - txgp revision 1.11 august 2003 - 14 - mcp memory sec only notes: 1. ra : read address, pa : program address, rd : read data, pd : program data da : dual bank address (a20 - a21), ba : block address (a12 - a21), x = don?t care . 2. to terminate the autoselect mode, it is necessary to write reset command to the register. 3. the 4th cycle data of autoselect mode is output data. the 3rd and 4th cycle bank addresses of autoselect mode must be same. 4. the read / program operations at non-erasing blocks and the autoselect mode are allowed in the erase suspend mode. 5. the erase suspend command is applicable only to the block erase operation. 6. command is valid when the device is in read mode or autoselect mode. 7. dq8 - dq15 are don?t care in command sequence, but rd and pd is excluded. 8. a11 - a21 are also don?t care, except for the case of special notice. table 6. nor flash memory autoselect codes notes: 1. l=logic low=v il , h=logic high=v ih , da=dual bank address, ba=block address, x=don?t care . 2. secode block : security code block. description dq8 to dq15 dq7 to dq0 byte = v ih byte = v il manufacturer id x x ech device code kab02d100 (top boot block) 22h x e0h device code kab01d100 (bottom boot block) 22h x e2h device code kab04d100 (top boot block) 22h x e1h device code kab03d100 (bottom boot block) 22h x e3h block protection verification x x 01h (protected), 00h (unprotected) secode block indicator bit (dq7) x x 80h (factory locked), 00h (not factory locked)
kab0xd100m - txgp revision 1.11 august 2003 - 15 - mcp memory sec only nand flash product introduction table 7. command sets function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o the nand flash memory is a 132mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 264 columns. spare 8 col- umns are located in 256 to 263 column address. a 264-word data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected like nand structure. each of the 16 cells resides in a different page. a block consists of the 32 pages formed by one nand structures, totaling 8,448 nand structures of 16 cells. the array organization is shown in figure 2. program and read operations are executed on a page basis, while erase operation is executed on a block basis. the memory array consists of 1024 blocks, and a block is separately erasable by 8k-word unit. it indicates that the bit by bit erase operation is prohi bited on the nand flash memory. the nand flash memory has addresses multiplexed with lower 8 i/o s. the nand flash memory allows sixteen bit wide data trans- fer into and out of page registers. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except page program command and block erase command which require two cycles: one cycle for setup and another for execution. the 8m word physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following required command input. in block erase operation, however, only two row address cycles are used. device operations are selected by writing specific com- mands into command register. table 7 defines the specific commands of the nand flash memory. table 8. nor flash operations table operation ce r oe we byte wp / acc a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset read word l l h h l/h a9 a6 a1 a0 dq15 d out d out h byte l l h l a9 a6 a1 a0 a-1 high-z d out h stand-by vcc r 0.3v x x x (2) x x x x high-z high-z high-z (2) output disable l h h x l/h x x x x high-z high-z high-z h reset x x x x l/h x x x x high-z high-z high-z l write word l h l h (4) a9 a6 a1 a0 d in d in d in h byte l h l l a9 a6 a1 a0 a-1 high-z d in h enable block group protect ( 3 ) l h l x l/h x l h l x x d in v id enable block group unprotect ( 3 ) l h l x (4) x h h l x x d in v id temporary block group x x x x (4) x x x x x x x v id
kab0xd100m - txgp revision 1.11 august 2003 - 16 - mcp memory sec only table 9. nand flash operations table note: 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce r we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/vcc f (2) stand-by table 10. u t ram operations table 1. x = v il or v ih cs u zz oe we lb ub i/o 0~7 i/o 8~15 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected deep power l h x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active notes: 1. l = v il (low), h = v ih (high), v id = 8.5v~12.5v, d in = data in, d out = data out, x = don't care. 2. wp /acc and reset pin are asserted at vcc r 0.3 v or vss 0.3 v in the stand-by mode. 3. addresses must be composed of the block address (a12 - a2 1 ). the block protect and unprotect operations may be implemented via programming equipment too. refer to the "block group protection and unprotection". 4 . if wp /acc = v il, the two outermost boot blocks is protected. if wp /acc = v ih, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "block group protection and unprotection". if wp /acc = v hh , all blocks will be temporarily unprotected.
kab0xd100m - txgp revision 1.11 august 2003 - 17 - mcp memory sec only nor flash device operation byte/word mode if the byte pin is set at logical "1" , the device is in word mode, dq0-dq15 are active. otherwise the byte pin is set at logical "0" , the device is in byte mode, dq0-dq7 are active. dq8-dq14 are in the high-z state and dq15 pin is used as an input for the lsb (a - 1) address pin. read mode the nor flash memory is controlled by chip enable ( ce r ), output enable ( oe ) and write enable ( we ). when ce r and oe are low and we is high, the data stored at the specified address location,will be the output of the device. the outputs are in high imped- ance state whenever ce r or oe is high. standby mode the nor flash memory features stand-by mode to reduce power consumption. this mode puts the device on hold when the device is deselected by making ce r high ( ce r = v ih ). refer to the dc characteristics for more details on stand-by modes. output disable the device outputs are disabled when oe is high ( oe = v ih ). the output pins are in high impedance state. automatic sleep mode the nor flash memory features automatic sleep mode to minimize the device power consumption. since the device typically draws 5 m a of the current in automatic sleep mode, this feature plays an extremely important role in battery-powered applications. when addresses remain steady for t aa +50ns, the device automatically activates the automatic sleep mode. in the sleep mode, output data is latched and always available to the system. when addresses are changed, the device provides new data without wait time. data outputs t aa + 50ns data auto sleep mode address data data data data figure 3. auto sleep mode operation autoselect mode the nor flash memory offers the autoselect mode to identify manufacturer and device type by reading a binary code. the autose- lect mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. in addition, this mode allows the verification of the status of write protected blocks. the manufacturer and device code can be read via the command register. the command sequence is shown in table 5 and figure 4. the autoselect operation of block pro- tect verification is initiated by first writing two unlock cycle. the third cycle must contain the bank address and autoselect c ommand (90h). if block address while (a6, a1, a0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at t he device output dq0 to indicate a write protected block or a logical "0" at the device output dq0 to indicate a write unprotected block. to ter- minate the autoselect operation, write reset command (f0h) into the command register.
kab0xd100m - txgp revision 1.11 august 2003 - 18 - mcp memory sec only figure 4. autoselect operation we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 90h 00h/ 01h/ ech manufacturer code device code a21 ~ a0(x16)/* dq15 ~ dq0 f0h return to read mode 22e0h or 22e2h note: the 3rd cycle and 4th cycle address must include the same bank address. please refer to table 6 for device code. a21 ~ a-1(x8) 00h 02h write (program/erase) mode the nor flash memory executes its program/erase operations by writing commands into the command register. in order to write the commands to the register, ce r and we must be low and oe must be high. addresses are latched on the falling edge of ce r or we (whichever occurs last) and the data are latched on the rising edge of ce r or we (whichever occurs first). the device uses standard microprocessor write timing. program the nor flash memory can be programmed in units of a word or a byte. programming is writing 0's into the memory array by exe- cuting the internal program routine. in order to perform the internal program routine, a four-cycle command sequence is neces- sary. the first two cycles are unlock cycles. the third cycle is assigned for the program setup command. in the last cycle, the address of the memory location and the data to be programmed at that location are written. the device automatically generates adequate p ro- gram pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the sy s- tem is not required to provide further controls or timings. during the internal program routine, commands written to the device will be ignored. note that a hardware reset during a program operation will cause data corruption at the corresponding location. ( kab02c100 / kab01c100) figure 5. program command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h a0h program program program start dq15-dq0 address data r/ b r a21 ~ a0(x16)/ a21 ~ a-1(x8)
kab0xd100m - txgp revision 1.11 august 2003 - 19 - mcp memory sec only unlock bypass the nor flash memory provides the unlock bypass mode to save its program time. the mode is invoked by the unlock bypass com- mand sequence. unlike the standard program command sequence that contains four bus cycles, the unlock bypass program com- mand sequence comprises only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. writ- ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. the unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the pro- gram address and data. this command sequence is the only valid one for programming the device in the unlock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command sequence consists of two bus cycles. the first cycle must contain the data (90h). the second cycle contains only the data (00h). then, the device returns to the read mode. chip erase to erase a chip is to write 1 s into the entire memory array by executing the internal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is written after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatically pre-programs and verifies th e entire memory for an all zero data pattern prior to erasing. the automatic erase begins on the rising edge of the last we or ce r pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. block erase to erase a block is to write 1 s into the desired memory block by executing the internal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 5. after the first two "unlock" cycles, the erase setup command (80h) is written at the third cycle. then there are two more "unlock" cycles followed by the block erase command. the internal erase rout ine automatically pre-programs and verifies the entire memory prior to erasing it. the block address is latched on the falling edge of we or ce r , while the block erase command is latched on the rising edge of we or ce r . multiple blocks can be erased sequentially by writing the six bus-cycle operation in fig 7. upon completion of the last cycle fo r the block erase, additional block address and the block erase command (30h) can be written to perform the multi-block erase. an 50us (typical) "time window" is required between the block erase command writes. the block erase command must be written within the 50us "time window", otherwise the block erase command will be ignored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the block erase command. during the 50us of "time window", any command other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 u s of "time window", the block erase command will initiate the internal erase routine to erase the selected blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command. figure 6. chip erase command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h chip erase start dq15-dq0 aaah 2aah/ 555h aah 55h 10h r/ b r 555h/ aaah a21 ~ a0(x16)/ a21 ~ a-1(x8)
kab0xd100m - txgp revision 1.11 august 2003 - 20 - mcp memory sec only we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h/ block erase start dq15-dq0 aaah 2aah/ 555h block address aah 55h 30h r/ b r we dq15-dq0 figure 8. erase suspend/resume command sequence erase suspend / resume the erase suspend command interrupts the block erase to read or program data in a block that is not being erased. the erase sus- pend command is only valid during the block erase operation including the time window of 50 m s. the erase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written during a block erase operation, the device requires a maximum of 20 m s to suspend the erase operation. but, when the erase suspend command is written during the block erase time window (50 m s) , the device imme- diately terminates the block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bein g erased. the system may also write the autoselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase operation will resume. when the erase suspend or erase resume command is executed, the addresses are in don't care state. figure 7. block erase command sequence a21 ~ a0(x16)/ a21a21 ~ a-1(x8) a21 ~ a0(x16)/ a21 ~ a-1(x8) 555h/ aaah block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence
kab0xd100m - txgp revision 1.11 august 2003 - 21 - mcp memory sec only read while write the nor flash memory provides dual bank memory architecture that divides the memory array into two banks. the device is capa- ble of reading data from one bank and writing data to the other bank simultaneously. this is so called the read while write oper ation with dual bank architecture; this feature provides the capability of executing the read operation during program/erase or erase- sus- pend-program operation. the read while write operation is prohibited during the chip erase operation. it is also allowed during erase operation when eit her single block or multiple blocks from same bank are loaded to be erased. it means that the read while write operation is prohibit ed when blocks from bank1 and another blocks from bank2 are loaded all together for the multi-block erase operation. block group protection & unprotection the nor flash memory feature hardware block group protection. this feature will disable both program and erase operations in any combination of forty one block groups of memory. please refer to tables 12 and 13. the block group protection feature is enabled using programming equipment at the user?s site. the device is shipped with all block groups unprotected. this feature can be hardware protected or unprotected. if a block is protected, program or erase command in the protected block will be ignored by the device. the protected block can only be read. this is useful method to preserve an important program data. the block group unprotection allows the protected blocks to be erased or programed. all blocks must be protected before unprotect op er- ation is executing. the block protection and unprotection can be implemented by the following method. table 11. block group protection & unprotection operation ce r oe we byte a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset block group protect l h l x x l h l x x d in v id block group unprotect l h l x x h h l x x d in v id address must be inputted to the block group address (a12~a21) during block group protection operation. please refer to figure 10 (algorithm) and switching waveforms of block group protect & unprotect operations. temporary block group unprotect the protected blocks of the nor flash memory can be temporarily unprotected by applying high voltage (v id = 8.5v ~ 12.5v) to the reset ball. in this mode, previously protected blocks can be programmed or erased with the program or erase command routines. when the reset ball goes high ( reset = v ih ), all the previously protected blocks will be protected again. if the wp /acc ball is asserted at v il , the two outermost boot blocks remain protected. reset program & erase operation v id v = v ih or v il at protected block ce r we figure 9. temporary block group unprotect sequence
kab0xd100m - txgp revision 1.11 august 2003 - 22 - mcp memory sec only figure 10. block group protection & unprotection algorithms note: all blocks must be protected before unprotect operation is executing. block protect algorithm set up block group address block group protect: write 60h to block group address with a6=0,a1=1 a0=0 wait 150 m s verify block group protect:write 40h to block group address with a6=0, a1=1,a0=0 read from block group address with a6=0, a1=1,a0=0 data=01h? protect another block group ? remove v id from reset write reset command end wait 1 m s first write cycle=60h? temporary block group unprotect mode block group unprotect write 60h with a6=1,a1=1 a0=0 wait 15ms verify block group unprotect:write 40h to block group address with a6= 1 , a1=1,a0=0 read from block group address with a6=1, a1=1,a0=0 data=00h? last block group remove v id from reset write reset command end no increment count count =1000? device failed no yes yes no no yes algorithm increment count count =25? device failed no yes no all block group s protected ? no block group , i= 0 start count = 1 reset =v id yes yes yes no verified ? block group protection ? yes no yes set up next block reset count=1 block unprotect group address
kab0xd100m - txgp revision 1.11 august 2003 - 23 - mcp memory sec only table 12. nor flash memory block group address (top boot block) block group block address block a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 bga0 0 0 0 0 0 0 0 x x x ba0 bga1 0 0 0 0 0 0 1 x x x ba1 to ba3 1 0 1 1 bga2 0 0 0 0 1 x x x x x ba4 to ba7 bga3 0 0 0 1 0 x x x x x ba8 to ba11 bga4 0 0 0 1 1 x x x x x ba12 to ba15 bga5 0 0 1 0 0 x x x x x ba16 to ba19 bga6 0 0 1 0 1 x x x x x ba20 to ba23 bga7 0 0 1 1 0 x x x x x ba24 to ba27 bga8 0 0 1 1 1 x x x x x ba28 to ba31 bga9 0 1 0 0 0 x x x x x ba32 to ba35 bga10 0 1 0 0 1 x x x x x ba36 to ba39 bga11 0 1 0 1 0 x x x x x ba40 to ba43 bga12 0 1 0 1 1 x x x x x ba44 to ba47 bga13 0 1 1 0 0 x x x x x ba48 to ba51 bga14 0 1 1 0 1 x x x x x ba52 to ba55 bga15 0 1 1 1 0 x x x x x ba56 to ba59 bga16 0 1 1 1 1 x x x x x ba60 to ba6 3 bga17 1 0 0 0 0 x x x x x ba64 to ba67 bga18 1 0 0 0 1 x x x x x ba68 to ba71 bga19 1 0 0 1 0 x x x x x ba72 to ba75 bga20 1 0 0 1 1 x x x x x ba76 to ba79 bga21 1 0 1 0 0 x x x x x ba80 to ba83 bga22 1 0 1 0 1 x x x x x ba84 to ba87 bga23 1 0 1 1 0 x x x x x ba88 to ba91 bga24 1 0 1 1 1 x x x x x ba92 to ba95 bga25 1 1 0 0 0 x x x x x ba96 to ba99 bga26 1 1 0 0 1 x x x x x ba100 to ba103 bga27 1 1 0 1 0 x x x x x ba104 to ba107 bga28 1 1 0 1 1 x x x x x ba108 to ba111 bga29 1 1 1 0 0 x x x x x ba112 to ba115 bga30 1 1 1 0 1 x x x x x ba116 to ba119 bga31 1 1 1 1 0 x x x x x ba120 to ba123 bga32 1 1 1 1 1 0 0 x x x ba124 to ba126 0 1 1 0 bga33 1 1 1 1 1 1 1 0 0 0 ba127 bga34 1 1 1 1 1 1 1 0 0 1 ba128 bga35 1 1 1 1 1 1 1 0 1 0 ba129 bga36 1 1 1 1 1 1 1 0 1 1 ba130 bga37 1 1 1 1 1 1 1 1 0 0 ba131 bga38 1 1 1 1 1 1 1 1 0 1 ba132 bga39 1 1 1 1 1 1 1 1 1 0 ba133 bga40 1 1 1 1 1 1 1 1 1 1 ba134
kab0xd100m - txgp revision 1.11 august 2003 - 24 - mcp memory sec only table 13. nor flash memory block group address (bottom boot block) block group block address block a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 bga0 0 0 0 0 0 0 0 0 0 0 ba0 bga1 0 0 0 0 0 0 0 0 0 1 ba1 bga2 0 0 0 0 0 0 0 0 1 0 ba2 bga3 0 0 0 0 0 0 0 0 1 1 ba3 bga4 0 0 0 0 0 0 0 1 0 0 ba4 bga5 0 0 0 0 0 0 0 1 0 1 ba5 bga6 0 0 0 0 0 0 0 1 1 0 ba6 bga7 0 0 0 0 0 0 0 1 1 1 ba7 bga8 0 0 0 0 0 0 1 x x x ba8 to ba10 1 0 1 1 bga9 0 0 0 0 1 x x x x x ba11 to ba14 bga10 0 0 0 1 0 x x x x x ba15 to ba18 bga11 0 0 0 1 1 x x x x x ba19 to ba22 bga12 0 0 1 0 0 x x x x x ba23 to ba26 bga13 0 0 1 0 1 x x x x x ba27 to ba30 bga14 0 0 1 1 0 x x x x x ba31 to ba34 bga15 0 0 1 1 1 x x x x x ba35 to ba38 bga16 0 1 0 0 0 x x x x x ba39 to ba42 bga17 0 1 0 0 1 x x x x x ba43 to ba46 bga18 0 1 0 1 0 x x x x x ba47 to ba50 bga19 0 1 0 1 1 x x x x x ba51 to ba54 bga20 0 1 1 0 0 x x x x x ba55 to ba58 bga21 0 1 1 0 1 x x x x x ba59 to ba62 bga22 0 1 1 1 0 x x x x x ba63 to ba66 bga23 0 1 1 1 1 x x x x x ba67 to ba70 bga24 1 0 0 0 0 x x x x x ba71 to ba74 bga25 1 0 0 0 1 x x x x x ba75 to ba78 bga26 1 0 0 1 0 x x x x x ba79 to ba82 bga27 1 0 0 1 1 x x x x x ba83 to ba86 bga28 1 0 1 0 0 x x x x x ba87to ba90 bga29 1 0 1 0 1 x x x x x ba91 to ba94 bga30 1 0 1 1 0 x x x x x ba95 to ba98 bga31 1 0 1 1 1 x x x x x ba99 to ba102 bga32 1 1 0 0 0 x x x x x ba103 to ba106 bga33 1 1 0 0 1 x x x x x ba107 to ba110 bga34 1 1 0 1 0 x x x x x ba111 to ba114 bga35 1 1 0 1 1 x x x x x ba115 to ba118 bga36 1 1 1 0 0 x x x x x ba119 to ba122 bga37 1 1 1 0 1 x x x x x ba123 to ba126 bga38 1 1 1 1 0 x x x x x ba127 to ba130 bga39 1 1 1 1 1 0 0 x x x ba131 to ba133 0 1 1 0 bga40 1 1 1 1 1 1 1 x x x ba134
kab0xd100m - txgp revision 1.11 august 2003 - 25 - mcp memory sec only write protect ( wp ) the wp /acc ball has two useful functions. the one is that certain boot block is protected by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph) . when the wp /acc ball is asserted at v il , the device can not perform program and erase operation in the two "outermost" 8k byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "block group pro- tection/unprotection". the write protected blocks can only be read. this is useful method to preserve an important program data. the two outermost 8k byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (kab02d100/kab04d100 : ba133 and ba134, kab01d100/kab03d100 : ba0 and ba1) when the wp /acc ball is asserted at v ih , the device reverts to whether the two outermost 8k byte boot blocks were last set to be protected or unprotected. that is, block protection or unprotection for these two blocks depends on whether they were last prote cted or unprotected using the method described in "block group protection/unprotection". recommend that the wp /acc ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunc- tion. accelerated program operation accelerated program operation reduces the program time through the acc function. this is one of two functions provided by the wp / acc ball. when the wp /acc ball is asserted as v hh , the device automatically enters the aforementioned unlock bypass mode, tem- porarily unprotecting any protected blocks, and reduces the program operation time. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp /acc ball returns the device to normal operation. recommend that the wp /acc ball must not be asserted at v hh except on accelerated program operation, or the device may be damaged. in addition, the wp /acc ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. software reset the reset command provides that the device is reseted to read mode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro- gram command sequence before programming begins. this resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequence. in the autoselect mode, the reset command returns the bank to read mode. if a bank entered the autoselect mode in the erase suspend mode, the reset command returns the bank to erase-suspend-read mode. if dq5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the erase suspend state. secode(security code) block region the secode block feature provides a nor flash memory region to be stored unique and permanent identification code, that is, elec - tronic serial number (esn), customer code and so on. this is primarily intended for customers who wish to use an electronic ser ial number (esn) in the device with the esn protected against modification. once the secode block region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the secode block is factory locked or customer lockable. before the device is shipped, the factory locked secode block is writte n on the special code and it is protected. the secode indicator bit (dq7) is permanently fixed at "1" and it is not changed. the customer lockable secode block is unprotected, therefore it is programmed and erased. the secode indicator bit (dq7) of it is permanently fixed at "0" and it is not changed. but once it is protected, there is no procedure to unprotect and modify the secode block. the secode block region is 64k bytes in length and is accessed through a new command sequence (see table 8). after the system has written the enter secode block command sequence, the system may read the secode block region by using the same addresses of the boot blocks (8kbx8). the kab02d100/kab04d100 occupies the address of the byte mode 7f0000h to 7fffffh (word mode 3f8000h to 3fffffh) and the kab01d100/kab03d100 type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh). this mode of operation continues until the system issues the exit secode block com- mand sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to read mode.
kab0xd100m - txgp revision 1.11 august 2003 - 26 - mcp memory sec only hardware reset the nor flash memory offers a reset feature by driving the reset ball to v il . the reset ball must be kept low (v il ) for at least 500ns. when the reset ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. if a hardware reset occurs during a program operation, the data at that particular location wil l be lost. once the reset ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output balls are tri-stated for the duration of the reset pulse. the reset ball may be tied to the system reset ball. if a system reset occurs during the internal program and erase routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware f rom the nor flash memory. power-up protection to avoid initiation of a write cycle during vcc r power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. low vcc r write inhibit to avoid initiation of a write cycle during vcc r power-up and power-down, a write cycle is locked out for vcc r less than 1.8v. if vcc r < v lko (lock-out voltage), the command register and all internal program/erase circuits are disabled. under this condition the device will reset itself to the read mode. subsequent writes will be ignored until the vcc r level is greater than v lko . it is the user s responsi- bility to ensure that the control balls are logically correct to prevent unintentional writes when vcc r is above 1.8v. write pulse glitch protection noise pulses of less than 5ns(typical) on ce r , oe , or we will not initiate a write cycle. logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce r = v ih or we = v ih . to initiate a write, ce r and we must be "0", while oe is "1". commom nor flash memory interface common flash momory interface is contrived to increase the compatibility of host system software. it provides the specific info rma- tion of the device, such as memory size, byte/word configuration, and electrical features. once this information has been obtain ed, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h in word mode(or address aah in byte mode), the device enters the cfi mode. and then if the system writes the address shown in table 14, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command.
kab0xd100m - txgp revision 1.11 august 2003 - 27 - mcp memory sec only table 14. common nor flash memory interface code description addresses (word mode) addresses (byte mode) data query unique ascii string "qry" 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h primary oem command set 13h 14h 26h 28h 0002h 0000h address for primary extended table 15h 16h 2ah 2ch 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 2eh 30h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 32h 34h 0000h 0000h vcc r min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 36h 0027h vcc r max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 38h 0036h vpp min. voltage(00h = no vpp pin present) 1dh 3ah 0000h vpp max. voltage(00h = no vpp pin present) 1eh 3ch 0000h typical timeout per single byte/word write 2 n us 1fh 3eh 0004h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 40h 0000h typical timeout per individual block erase 2 n ms 21h 42h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 44h 0000h max. timeout for byte/word write 2 n times typical 23h 46h 0005h max. timeout for buffer write 2 n times typical 24h 48h 0000h max. timeout per individual block erase 2 n times typical 25h 4ah 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 4ch 0000h device size = 2 n byte 27h 4eh 0017h flash device interface description 28h 29h 50h 52h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 54h 56h 0000h 0000h number of erase block regions within device 2ch 58h 0002h erase block region 1 information 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 62h 64h 66h 68h 007eh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h
kab0xd100m - txgp revision 1.11 august 2003 - 28 - mcp memory sec only table 14. common nor flash memory interface code note: 1. the number of blocks in bank2 is device dependent. kab02d100/kab04d100(16mb/48mb) = 60h (96blocks) kab01d100/kab03d100(32mb/32mb ) = 40h (64blocks) description addresses (word mode) addresses (byte mode) data query-unique ascii string "pri" 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h major version number, ascii 43h 86h 0030h minor version number, ascii 44h 88h 0030h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 8ah 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 8ch 0002h block protect 0 = not supported, 1 = supported 47h 8eh 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 90h 0001h block protect/unprotect scheme 04 = k8d1x16u mode 49h 92h 0004h simultaneous operation (1) 00 = not supported, xx = number of blocks in bank2 4ah 94h 00xxh burst mode type 00 = not supported, 01 = supported 4bh 96h 0000h page mode type 00=not supported, 01=4word page, 02=8word page 4ch 98h 0000h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 9ah 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 9ch 00c5h top/bottom boot block flag 02h = bottom boot , 03h = top boot 4fh 9eh 000xh
kab0xd100m - txgp revision 1.11 august 2003 - 29 - mcp memory sec only nor flash device status flags the nor flash memory has means to indicate its status of operation in the bank where a program or erase operation is in pro- cesses. address must include bank address being excuted internal routine operation. the status is indicated by raising the devic e status flag via corresponding dq balls or the r/ b r ball. the corresponding dq balls are dq7, dq6, dq5, dq3 and dq2. the status is as follows : table 15. hardware sequence flags notes: 1. dq2 will toggle when the device performs successive read operations from the erase suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. status dq7 dq6 dq5 dq3 dq2 r/ b r in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1 1 0 0 toggle (note 1) 1 erase suspend read non-erase sus- pended block data data data data data 1 erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 dq7 : data polling when an attempt to read the device is made while executing the internal program, the complement of the data is written to dq7 as an indication of the routine in progress. when the routine is completed an attempt to access to the device will produce the true data written to dq7. when a user attempts to read the device during the erase operation, dq7 will be low. if the device is placed in the erase suspend mode, the status can be detected via the dq7 ball. if the system tries to read an address which belongs to a block that is being erased, dq7 will be high. if a non-erased block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 m s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement data in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy sta te, dq6 will toggle. toggling dq6 will stop after the device completes its internal routine. if the device is in the erase suspend m ode, an attempt to read an address that belongs to a block that is being erased will produce a high output of dq6. if an address belo ngs to a block that is not being erased, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggles for approximately 1us and the device then returns to the read mo de without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 m s and the device then returns to the read mode without erasing the data in the block. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timing limits, dq5 will go high, indicating program/erase failure.
kab0xd100m - txgp revision 1.11 august 2003 - 30 - mcp memory sec only r/ b r : ready/ busy the nor flash memory has a ready / busy output that indicates either the completion of an operation or the status of internal algo- rithms. if the output is low, the device is busy with either a program or an erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the r/ b r pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend command. if the nor flash memory is placed in an erase suspend mode, the r/ b r output will be high. for programming, the ry/ by is valid (r/ b r = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, r/ b r is also valid after the rising edge of we pulse in the six write pulse sequence. for block erase, r/ b r is also valid after the rising edge of the sixth we pulse. the pin is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up resistor is required for proper operation. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 m s of the block erase time win- dow expires. in this case, the internal erase routine will initiate the erase operation.therefore, the device will not accept fu rther write commands until the erase operation is completed. dq3 is low if the block erase time window is not expired. within the block eras e time window, an additional block erase command (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq2 only if an internal erase routine or an erase suspend is in progress. when the devi ce executes the internal erase routine, dq2 toggles only if an erasing block is read. although the internal erase routine is in the exceeded time limits, dq2 toggles only if an erasing block in the exceeded time limits is read. when the device is in the erase suspend mode, dq2 toggles only if an address in the erasing block is read. if a non-erasing block address is read during the era se suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend block while th e device is in the erase suspend mode. combination of the status in dq6 and dq2 can be used to distinguish the erase operation from the program operation. rp = vcc ready / busy open drain output device vss vcc (max.) - v ol (max.) i ol + s i l = 2.7 v 2.1ma + s i l where s i l is the sum of the input currents of all devices tied to the ready / busy pin. rp
kab0xd100m - txgp revision 1.11 august 2003 - 31 - mcp memory sec only start dq7 = data ? no dq5 = 1 ? fail pass start dq6 = toggle ? no dq5 = 1 ? dq6 = toggle ? fail pass no no yes yes yes yes figure 13. temporary block group unprotect routine start reset =v id notes: 1. all protected block group s are unprotected. ( if wp /acc = v il , the two outermost boot blocks remain protected ) 2. all previously protected block group s are protected once again. (note 1) perform erase or program operations temporary block unprotect completed (note 2) reset =v ih figure 11. data polling algorithms figure 12. toggle bit algorithms dq7 = data ? no yes no yes
kab0xd100m - txgp revision 1.11 august 2003 - 32 - mcp memory sec only nand flash memory operation page read upon initial device power up, the device status is initially read1 command(00h) latched. this operation is also initiated by wr iting 00h to the command register along with three address cycles. once the command is latched, it does not need to be written for the fol- lowing page read operation. two types of operation are available : random read, serial page read. the random read mode is enable d when the page address is changed. the 264 words of data within the selected page are transferred to the data registers in less t han 10 m s(tr). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out by sequential re pulse of 50n period cycle. high to low transitions of the re clock take out the data from the selected column address up to the last column address. read1 and read2 commands determine pointer which selects either main area or spare area. the spare area(256 to 263 words) may be selectively accessed by writing the read2 command. addresses a 0 to a 2 set the starting address of spare area while addresses a 3 to a 7 must be "l". to move the pointer back to the main area, read1 command(00h) is needed. figures 16 through 21 show typical sequence and timing for each read operation. figure 14,15 details the sequence. figure 14. read1 operation start add.(3cycle) 00h data output(sequential) ce cle ale r/ b f we dq x re t r
kab0xd100m - txgp revision 1.11 august 2003 - 33 - mcp memory sec only page program the device is programmed basically on a page basis, but it allows multiple partial page program of one word or consecutive words up to 264, in a single page program cycle. the number of consecutive partial page program operation within the same page without intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. page program cycle consists of a serial data loading(up to 264 words of data) into the page register, and prog ram of loaded data into the appropriate cell. serial data loading can start in 2nd half array by moving pointer. about the pointer oper ation, please refer to the attached technical notes. serial data loading is executed by entering the serial data input command(80h) and three cycle address input and then serial data loading. the bytes except those to be programmed need not to be loaded. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering 80h will not initi ate program process. the internal write controller automatically executes the algorithms and timings necessary for program and verif ica- tion, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b out- put, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is completed, the write status bit(i/o 0) may be checked(figure 16). the internal write ve ri- fication detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 16 details the sequence. figure 16. program & read status operation 80h dq x r/ b f address & data input dq 0 pass 10h 70h fail t prog figure 15. read2 operation 50h a 0 ~ a 2 & a 9 ~ a 23 data output(sequential) spare field ce cle ale r/ b f we data field spare field start add.(3cycle) (a 3 ~ a 7 : "l") dq x re t r
kab0xd100m - txgp revision 1.11 august 2003 - 34 - mcp memory sec only figure 17. block erase operation block erase the erase operation is done on a block(16k bytes) basis. block erase is executed by entering erase setup command(60h) and 2 cycle block addresses and erase confirm command(d0h). only address a14 to a23 is valid while a9 to a13 is ignored. this two- step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition. at the rising edge of we after erase confirm command input, internal write controller handles erase and erase-ver- ification. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 6 details the sequence. 60h block add. : a 9 ~ a 23 dq x r/ b f address input(2cycle) dq 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to command register, a read cycle takes out the content of the status register to the i/o pins on the falling edge of ce f or re . this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce f does not need to be toggled for updated status. refer to table 16 for specific status register definitions. the command register remains in status r ead mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, a read com- mand(00h or 50h) should be given before sequential page read cycle. table 16. read status register definition dq # status definition dq 0 program / erase "0" : successful program / erase "1" : error in program / erase dq 1 reserved for future use "0" dq 2 "0" dq 3 "0" dq 4 "0" dq 5 "0" dq 6 device operation "0" : busy "1" : ready dq 7 write protect "0" : protected "1" : not protected dq 8~15 not use don?t care
kab0xd100m - txgp revision 1.11 august 2003 - 35 - mcp memory sec only figure 18. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (53h) respectively. the command regis- ter remains in read id mode until further commands are issued to it. figure 18 shows the operation sequence. figure 19. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 17 for device status after reset operation. if the device is already in reset state, new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. reset command is not necessary for normal operation. refer to figure 19 below. table 17. device status after power-up after reset operation mode read 1 waiting for next command ffh dq x r/ b f t rst ce f cle i/o x ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar1 t rea 53h t whr
kab0xd100m - txgp revision 1.11 august 2003 - 36 - mcp memory sec only ready/ busy the device has a r/ b f output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b f pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b f outputs to be or-tied. because pull-up resistor value is related to tr(r/ b f ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 20). its val ue can be determined by the following guidance. vcc r r/ b f open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp = v cc (max.) - v ol (max.) i ol + s i l = 2.7v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v figure 20. rp vs tr ,tf & rp vs ibusy
kab0xd100m - txgp revision 1.11 august 2003 - 37 - mcp memory sec only the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc f is below about 1.3v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any com- mand sequences as shown in figure 21. the two step command sequence for program/erase provides additional software protec- tion. figure 21. ac waveforms for power transition v cc f wp high ? ? we ~ 2.5v ~ 2.5v ? 10 m s data protection & powerup sequence
kab0xd100m - txgp revision 1.11 august 2003 - 38 - mcp memory sec only identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding invalid block(s) is so called as the invalid block information. devices ,regardless of having invalid block(s), have the same quality level because all valid blocks have same ac and dc characteristics. an invalid block(s) does not affect the perfor - mance of valid block(s) because it?s bit line and common source line is isolated by a select transistor. the system design must be able to mask out invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 1st and 6th word in the spare area. samsung makes sure that either 1st and 2nd page of every invalid block has non-ffffh data at the column address of 256 and 261. since invalid block information is also erasable in most cases, it is impossible to recover the information once it was erased. therefore, system must be able to recognize the invalid b lock(s) based on the original invalid block information and create invalid block table via the following suggested flow chart(figure 22) . any intentional erasure of the original invalid block information is prohibited. * figure 22. flow chart to create invalid block table start set block address = 0 check "ffffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table check "ffffh" at the column address 256 and 261of the 1st and 2nd page nand flash technical notes in the block
kab0xd100m - txgp revision 1.11 august 2003 - 39 - mcp memory sec only error in write operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for act ual data. the following possible failure modes should be considered to implement a highly reliable system. in the case of status rea d fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. the said additional block fail ure rate does not include those reclaimed blocks. note: 1. if program/erase cycles is under 1k, single bilt failure do not occure. therefore there is no need to provide ecc. 2. ecc -> error correction code -> hamming code etc. example) 1bit error correction and 2 bit error detection failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement read single bit failure (1) verify ecc -> ecc correction (2) nand flash technical notes figure 24. flash program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used or program/erase cycles are under 1k, write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * this verification operation is not needed.
kab0xd100m - txgp revision 1.11 august 2003 - 40 - mcp memory sec only figure 24. flash erase flow chart start dq 6 = 1 ? dq 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes nand flash technical notes figure 25. block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the 1st ~ (n-1)th data to the same location of the block ?b?. * step4 do not further erase block ?a? by creating a ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~
kab0xd100m - txgp revision 1.11 august 2003 - 41 - mcp memory sec only samsung nand flash(x16) has two address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255word), and ?50h? command sets the pointer to ?b? area(256~263word). with these com- mands, the starting column address can be set to any of a whole page(0~263word). ?00h? or ?50h? is sustained until another addre ss pointer command is inputted. to program data starting from ?a? or ?b? area, ?00h? or ?50h? command must be inputted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 50h (2) command input sequence for programming ?b? area address / data input 80h 10h 50h 80h 10h address / data input only ?b? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?b? area(256~263), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b? area can be programmed. pointer operation of nand flash table 18. destination of the pointer command pointer position area 00h 50h 0 ~ 255 word 256 ~ 263 word main array(a) spare array(b) "a" area 256 word (00h plane) "b" area (50h plane) 8 word "a" "b" internal page register pointer select commnad (00h, 50h) pointer figure 26. block diagram of pointer operation nand flash technical notes
kab0xd100m - txgp revision 1.11 august 2003 - 42 - mcp memory sec only nand flash technical notes ce f we t wp t ch t cs start add.(3cycle) 80h data input ce f cle ale we dq x data input ce f don?t-care ? ? 10h for an easier system interface, ce f may be inactive during data-loading or sequential data-reading as shown below. the internal 264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce f during the data-loading and read- ing would provide significant saving in power consumption. start add.(3cycle) 00h ce f cle ale we dq x data output(sequential) ce f don?t-care ? r/ b f t r re t cea out t rea ce f re i/o 0 ~ 7 figure 27. program operation with ce f don?t-care. figure 28. read operation with ce f don?t-care. system interface using ce don?t-care.
kab0xd100m - txgp revision 1.11 august 2003 - 43 - mcp memory sec only absolute maximum ratings note: 1. minimum dc voltage is -0.2v on input/output balls. during transitions, this level may undershoot to -1.0v for periods <20ns. maximum dc voltage on input/output balls is v cc +0.3v which, during transitions, may overshoot to v cc +1.0v for periods <20ns. 2. minimum dc voltage is -0.2v on reset and wp /acc balls. during transitions, this level may undershoot to -1.0v for periods <20ns. maximum dc voltage on on reset and wp /acc balls is 12.5v which, during transitions, may overshoot to 14.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc r ,vcc f ,vcc u ,vccq u -0.2 to vcc+0.3 v reset v in -0.2 to 12.5v wp /acc -0.2 to 12.5v other balls -0.2 to 3.6v temperature under bias t bias -40 to + 125 c storage temperature t stg -65 to + 150 operating temperature t a -25 to + 85 recommended operating conditions (voltage reference to vss, t a =-25 to 85 c) parameter symbol min typ. max unit supply voltage vcc r ,vcc f ,vcc u ,vccq u 2.7 2.9 3.1 v supply voltage v ss 0 0 0 v dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min max unit input leakage current i li v in =vss to vcc, vcc=vcc max -10 10 m a output leakage current i lo v out =vss to vcc, vcc=vcc max, oe =v ih -10 10 m a input low voltage level v il -0.3 0.5 v input high voltage level v ih 2.2 vcc+0.3 output low voltage level v ol i ol = 2.1ma, vcc = vcc min - 0.4 output high voltage level v oh i oh = -1.0ma, vcc = vcc min 2.3 -
kab0xd100m - txgp revision 1.11 august 2003 - 44 - mcp memory sec only dc and operating characteristics notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component(at 5 mhz). the read current is typically 14 ma (@ vcc r =2.9v , oe at v ih .) 2. i cc active during internal routine(program or erase) is in progress. 3. i cc active during read while write is in progress. 4. the high voltage ( v hh or v id ) must be used in the range of vcc r = 2.9v 0.2v 5. not 100% tested. 6. typical values are measured at vcc = 2.9v, ta=25 c, not 100% tested. parameter symbol test conditions min typ max unit nor flash reset input leakage current i lit vcc r =vcc r max, reset =12.5v - - 35 m a wp/ acc input leakage current i liw vcc r =vcc r max, wp/ acc=12.5v - - 35 m a active read current (1) i cc 1 ce r =v il , oe =v ih 5mhz - 14 20 ma 1mhz - 3 6 active write current (2) i cc 2 ce r =v il , oe =v ih - 15 30 ma read while program current (3) i cc 3 ce r =v il , oe =v ih - 25 50 ma read while erase current (3) i cc 4 ce r =v il , oe =v ih - 25 50 ma program while erase suspend current i cc 5 ce r =v il , oe =v ih - 15 35 ma acc accelerated program current i acc ce r =v il , oe =v ih acc ball - 5 10 ma vcc r ball - 15 30 ma standby current i sb 1 vcc r =vcc r max, ce r =vcc r 0.3v, reset =vcc r 0.3v, wp /acc=vcc r 0.3v or vss 0.3v - 10 30 m a standby curren during reset i sb 2 vcc r =vcc r max , reset =vss 0.3v, wp /acc=vcc r 0.3v or vss 0.3v - 10 30 m a automatic sleep mode i sb 3 v ih =vcc r 0.3v, v il =vss 0.3v, oe =v il , i ol =i oh =0 - 10 30 m a voltage for wp /acc block temporarily unprotect and program acceleration (4) v hh vcc r = 2.9v 0.2v 8.5 - 12.5 v voltage for autoselect and block protect (4) v id vcc r = 2.9v 0.2v 8.5 - 12.5 v low vcc r lock-out voltage (5) v lko 1.8 - 2.5 v nand flash active sequential read currnt i cc 1f trc=50ns, ce f =v il , i out =0ma, vcc f =vcc f max - 10 20 ma active program current i cc 2f vcc f =vcc f max - 10 20 ma active erase current i cc 3f vcc f =vcc f max - 10 20 ma stand_by current(cmos) i sb 2f ce f =vcc f , wp =0v/vcc f - 10 50 m a u t ram operating current i cc 1u cycle time=1 m s, 100% duty, i io =0ma, cs u 0.2v, zz 3 vccq u -0.2v, v in 0.2v or v in 3 vccq u -0.2v - 4 7 ma i cc 2u cycle time=min, 100% duty, i io =0ma, cs u =vil, zz =v ih , v in =v il or v ih - 30 35 ma stand_by current(cmos) i sb 2u cs u 3 vccq u -0.2v, zz 3 vccq u -0.2v, other inputs =0~vccq u - 80 100 m a deep power down i sbd zz 0.2v, other input =0~vccq u - 5 10 m a
kab0xd100m - txgp revision 1.11 august 2003 - 45 - mcp memory sec only capacitance (t a = 25 c, v cc = 2.9v, f = 1.0mhz) note: capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 28 pf input/output capacitance c io v io =0v - 30 pf valid block of nand flash memory note: 1. the nand flash memory may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not try to access these invalid blocks for program and erase. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correcti on. parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks zz =v il cs u =v ih zz =v il cs u =v il , ub or/and lb =v il zz =v ih cs u =v ih , zz =v ih standby mode state machines(u t ram) read operation twice power on initial state (wait 200 m s) active standby mode deep power down mode standby mode characteristic(u t ram) power mode memory cell data standby current( m m a) wait time( m m s) standby valid 100 0 deep power down invaild 10 200 zz =v ih cs u =v ih ac test condition note: ac test inputs are driven at vcc r , vcc f or vcc u for a logic "1" and 0v for a logic "0". input timing begins, and output timing ends, at vcc r /2, vcc f /2 or vccq u /2. input rise and fall times (10% - 90%)<5ns. worst case speed condition are when vcc r = vcc r min, vcc f = vcc f min or vccq u = vccq u min. parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 or vccq u /2 output load c l = 30pf 0v vcc vcc/2 vcc/2 or vccq u /2 input pulse and test point input & output test point output load * c l = 30pf including scope c l device and jig capacitance
kab0xd100m - txgp revision 1.11 august 2003 - 46 - mcp memory sec only alternate we controlled write notes: 1. not 100% tested. 2. the duration of the program or erase operation varies and is calculated in the internal algorithms. parameter symbol 70ns 80ns unit min max min max write cycle time (1) t wc 70 - 80 - ns address setup time t as 0 - 0 - ns t aso 55 - 55 - ns address hold time t ah 45 - 45 - ns t aht 0 - 0 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns output enable setup time (1) t oes 0 - 0 - ns output enable hold time read (1) t oeh1 0 - 0 - ns toggle and data polling (1) t oeh2 10 - 10 - ns ce r setup time t cs 0 - 0 - ns ce r hold time t ch 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) sec vcc r set up time t vcs 50 - 50 - m s write recovery time from r/ b r t rb 0 - 0 - ns reset high time before read t rh 50 - 50 - ns reset to power down time t rpd 20 - 20 - m s program/erase valid to r/ b r delay t busy 90 - 90 - ns v id rising and falling time t vid 500 - 500 - ns reset pulse width t rp 500 - 500 - ns reset low to r/ b r high t rrb - 20 - 20 m s reset setup time for temporary unprotect t rsp 1 - 1 - m s reset low setup time t rsts 500 - 500 - ns reset high to address valid t rstw 200 - 200 - ns read recovery time before write t ghwl 0 - 0 - ns ce high during toggling bit polling t ceph 20 - 20 - ns oe high during toggling bit polling t oeph 20 - 20 - ns write(erase/program)operations nor flash ac characteristics
kab0xd100m - txgp revision 1.11 august 2003 - 47 - mcp memory sec only nor flash ac characteristics write(erase/program)operations alternate ce r controlled writes notes: 1. not 100% tested. 2.this does not include the preprogramming time. parameter symbol 70ns 80ns unit min max min max write cycle time (1) t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns output enable setup time (1) t oes 0 - 0 - ns output enable hold time read (1) t oeh1 0 - 0 - ns toggle and data polling (1) t oeh2 10 - 10 - ns we setup time t ws 0 - 0 - ns we hold time t wh 0 - 0 - ns ce r pulse width t cp 35 - 35 - ns ce r pulse width high t cph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) sec byte switching low to output high-z t flqz 25 - 25 - ns erase and program performance notes: 1. 25 c, vcc r = 2.9v 100,000 cycles, typical pattern . 2. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte . in the preprogramming step of the internal erase routine, all bytes are programmed to 00h before erasure. parameter limits unit comments min typ max block erase time - 0.7 15 sec excludes 00h programming prior to erasure chip erase time - 98 - sec word programming time - 14 330 m s excludes system-level overhead byte programming time - 9 210 m s excludes system-level overhead accelerated byte/word program time word mode - 9 210 m s excludes system-level overhead byte mode - 7 150 m s excludes system-level overhead chip programming time word mode - 59 177 sec excludes system-level overhead byte mode - 75 225 sec erase/program endurance 100,000 - - cycles minimum 100,000 cycles guaran- teed
kab0xd100m - txgp revision 1.11 august 2003 - 48 - mcp memory sec only read operations nor flash switching waveforms oe address t ce t oeh1 ce r outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df r/ b r high note: 1. not 100% tested. parameter symbol 70ns 80ns unit min max min max read cycle time t rc 70 - 80 - ns address access time t aa - 70 - 80 ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce r & oe disable time (1) t df - 16 - 16 ns output hold time from address, ce r or oe t oh 0 - 0 - ns oe hold time t oeh1 0 - 0 - ns
kab0xd100m - txgp revision 1.11 august 2003 - 49 - mcp memory sec only hardware reset/read operations nor flash switching waveforms parameter symbol 70ns 80ns unit min max min max read cycle time t rc 70 - 80 - ns address access time t aa - 70 - 80 ns chip enable access time t ce - 70 - 80 ns output hold time from address, ce r or oe t oh 0 - 0 - ns reset pulse width t rp 500 - 500 - ns reset high time before read t rh 50 - 50 - ns reset address ce r outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid
kab0xd100m - txgp revision 1.11 august 2003 - 50 - mcp memory sec only alternate we controlled program operations nor flash switching waveforms notes: 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address t cs ce r data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t oes t pgm status dout 555h pa pa a0h data polling t ch pd t wph r/ b r t busy t rb t wc parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns ce r setup time t cs 0 - 0 - ns ce r hold time t ch 0 - 0 - ns oe setup time t oes 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) us byte 9(typ.) 9(typ.) us accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s read cycle time t rc 70 - 80 - ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce r & oe disable time t df - 16 - 16 ns output hold time from address, ce r or oe t oh 0 - 0 - ns program/erase valide to r/ b r delay t busy 90 - 90 - ns recovery time from r/ b r t rb 0 - 0 - ns
kab0xd100m - txgp revision 1.11 august 2003 - 51 - mcp memory sec only alternate ce r controlled program operations nor flash switching waveforms notes: 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address we data ce r t ah t as t ds t dh t cp t oes a0h 555h pa pa status dout data polling t cph t ws t pgm r/ b r t busy t rb pd t wc parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns oe setup time t oes 0 - 0 - ns we setup time t ws 0 - 0 - ns we hold time t wh 0 - 0 - ns ce r pulse width t cp 35 - 35 - ns ce r pulse width high t cph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s program/erase valide to r/ b r delay t busy 90 - 90 - ns recovery time from r/ b r t rb 0 - 0 - ns
kab0xd100m - txgp revision 1.11 august 2003 - 52 - mcp memory sec only nor flash switching waveforms parameter symbol 70ns 80ns unit min max min max chip enable access time t ce - 70 - 80 ns ce r to byte switching low or high t elfl /t elfh - 5 - 5 ns byte switching low to output high-z t flqz - 25 - 25 ns byte switching high to output active t fhqv - 25 - 25 ns oe t flqz ce r dq0-dq7 byte we byte timing diagram for write operation the falling edge of the last we signal ce r byte t hold (t ah ) dq15/a-1 t elfl address input (a-1) t set (t as ) word to byte timing diagram for read operation byte to word timing diagram for read operation data output (dq0-dq7) dq8-dq14 data output (dq8-dq14) data output (dq15) oe t fhqv ce r dq0-dq7 byte dq15/a-1 t elfh data output dq8-dq14 address input (a-1) data output (dq8-dq14) (dq15) t ce t ce data output (dq0-dq7)
kab0xd100m - txgp revision 1.11 august 2003 - 53 - mcp memory sec only nor flash switching waveforms chip/block erase operations parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns oe setup time t oes 0 - 0 - ns ce r setup time t cs 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns read cycle time t rc 70 - 80 - ns vcc r set up time t vcs 50 - 50 - m s oe address t cs ce r data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp t oes 55h r/ b r t wc t vcs vcc r note: ba : block address
kab0xd100m - txgp revision 1.11 august 2003 - 54 - mcp memory sec only read while write operations nor flash switching waveforms parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns read cycle time t rc 70 - 80 - ns chip enable access time t ce - 70 - 80 ns address access time t aa - 70 - 80 ns output enable access time t oe - 25 - 25 ns oe setup time t oes 0 - 0 - ns oe hold time t oeh2 10 - 10 - ns ce r & oe disable time t df - 16 - 16 ns address hold time t aht 0 - 0 - ns ce r high during toggle bit polling t ceph 20 - 20 - ns note: this is an example in the program-case of the read while write function. d a1 : address of bank1, da2 : address of bank 2 pa = program address at one bank , ra = read address at the other bank , pd = program data in , rd = read data out oe ce r dq we t rc read command command read read read t ah t aa t ce t as t aht t as t ceph t oe t oes t wp t oeh2 t df t ds t dh t df da1 da2 da1 da1 da2 da2 (555h) ( pa ) ( pa ) valid output valid output valid in put valid output valid in put status address (a0h) (pd) t rc t rc t rc t wc t wc
kab0xd100m - txgp revision 1.11 august 2003 - 55 - mcp memory sec only data polling during internal routine operation nor flash switching waveforms parameter symbol 70ns 80ns unit min max min max program/erase valid to r/ b r delay t busy 90 - 90 - ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce r & oe disable time t df - 16 - 16 ns output hold time from address, ce r or oe t oh 0 - 0 - ns oe hold time t oeh2 10 - 10 - ns oe t ce t oeh2 ce r dq7 we t oe high-z t df note: *dq7=vaild data (the device has completed the internal operation). dq7 *dq7 = valid data t oh t pgm or t bers high-z valid data dq0-dq6 data in data in we r/ b r timing diagram during program/erase operation the rising edge of the last we signal ce r r/ b r t busy entire progrming or erase operation status data
kab0xd100m - txgp revision 1.11 august 2003 - 56 - mcp memory sec only toggle bit during internal routine operation nor flash switching waveforms t dh ce r address* oe dq6/dq2 we r/ b r data in t aht t aht t aso t as t ceph t oeh2 t oeph status data t o e status data status data array data out note: address for the write operation must include a bank address (a20~a21) where the data is written. dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read note: dq2 is read from the erase-suspended block. toggle dq 2 and dq 6 with oe or ce r parameter symbol 70ns 80ns unit min max min max output enable access time t oe - 25 - 25 ns oe hold time t oeh2 10 - 10 - ns address hold time t aht 0 - 0 - ns address setup t aso 55 - 55 - ns address setup time t as 0 - 0 - ns data hold time t dh 0 - 0 - ns ce r high during toggle bit polling t ceph 20 - 20 - ns oe high during toggle bit polling t oeph 20 - 20 - ns
kab0xd100m - txgp revision 1.11 august 2003 - 57 - mcp memory sec only reset timing diagram nor flash switching waveforms parameter symbol 70ns 80ns unit min max min max reset pulse width t rp 500 - 500 - ns reset low to valid data (during internal routine) t ready - 20 - 20 m s reset low to valid data (not during internal routine) t ready - 500 - 500 ns reset high time before read t rh 50 - 50 - ns r/ b r recovery time t rb 0 - 0 - ns reset high to address valid t rstw 200 - 200 - ns reset low set-up time t rsts 500 - 500 - ns reset t rp power-up and reset timing diagram ce r or oe r/ b r t ready t rb reset ce r or oe r/ b r t rh t ready t rp reset timings not during internal routine reset timings during internal routine high reset t aa vcc address data t rsts
kab0xd100m - txgp revision 1.11 august 2003 - 58 - mcp memory sec only block group protect & unprotect operations nor flash switching waveforms ce r temporary block group unprotect program or erase command sequence r eset we t rsp r/ b r t vid v id v ss ,v il , or v ih v ss ,v il , or v ih t rrb t vid bga,a6 a1,a0 reset ce r we d ata oe v ss ,v il , 60h 60h 40h status* block group protect / unprotect verify 1 m s block group protect:150 m s block group unprotect:15ms notes: block group protect (a6= v il , a1= v ih , a0= v il ) , status=01h block group unprotect (a6= v ih , a1= v ih , a0= v il ) , status=00h bga = block group address (a12 ~ a21) r/ b r v id valid valid valid t busy t rb or v ih v ss ,v il , or v ih
kab0xd100m - txgp revision 1.11 august 2003 - 59 - mcp memory sec only nand flash ac characteristics for operation (vcc f =2.7~3.1v, t a =-25 to 85 c) note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 10 - ns ce f access time t cea - 45 ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 30 ns re high to output hi-z t rhz - 30 ns ce f high to output hi-z t chz - 20 ns re or ce f high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s (vcc f =2.7~3.1v, t a =-25 to 85 c) parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce f setup time t cs 0 - ns ce f hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns nand flash program/erase characteristics (vcc f =2.7~3.1v, t a =-25 to 85 c) parameter symbol min typ max unit program time t prog - 200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms nand flash ac timing characteristics for command/address/data input
kab0xd100m - txgp revision 1.11 august 2003 - 60 - mcp memory sec only nand flash command latch cycle ce f we cle ale dq x command t cls t cs t clh t ch t wp t als t alh t ds t dh nand flash address latch cycle ce f we cle ale dq x a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 23 t wp t ds t dh t alh
kab0xd100m - txgp revision 1.11 august 2003 - 61 - mcp memory sec only nand flash input data latch cycle ce f cle we dq x din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp ? ? ? nand flash sequential out cycle after read (cle=l, we =h, ale=l) re ce f r/ b f dq x dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz* ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t rp t oh t oh
kab0xd100m - txgp revision 1.11 august 2003 - 62 - mcp memory sec only nand flash status read cycle ce f we cle re dq x 70h status output t cls t clh t cs t wp t ch t ds t dh t rea t ir t rhz* t chz* t whr t cea t cls nand flash read1 operation (read one page) ce f cle r/ b f dq x we ale re busy 00h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar t r t rc t rhz t chz dout 264 t wc t rr ? ? ? t oh t oh t oh t oh
kab0xd100m - txgp revision 1.11 august 2003 - 63 - mcp memory sec only nand flash read2 operation (read one page) ce f cle r/ b f dq x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout dout 264 m address a 0 ~ a 2 : valid address a 3 ~ a 7 : "l" 256+m dout 256+m+1 t ar t r t wb t rr ? ? ? selected row start address m 256 8 nand flash page program operation ce f cle r/ b f dq x we ale re 80h 70h dq 0 din n din din 10h 264 n+1 a 0 ~ a 7 a 17 ~ a 23 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 264 word data serial input program command read status command dq 0 =0 successful program dq 0 =1 error in program t prog t wb t wc t wc t wc ? ? ?
kab0xd100m - txgp revision 1.11 august 2003 - 64 - mcp memory sec only nand flash manufacture & device id read operation ce f cle dq x we ale re 90h read id command maker code device code 00h ech 73h t rea address 1st cycle nand flash block erase operation (erase one block) ce f cle r/ b f dq x we ale re 60h a 17 ~ a 23 a 9 ~ a 16 auto block erase erase command read status command dq 0 =1 error in erase doh 70h dq 0 busy t wb t bers dq 0 =0 successful erase page(row) address t wc ? setup command t ar
kab0xd100m - txgp revision 1.11 august 2003 - 65 - mcp memory sec only u t ram ac characteristics (vcc u =2.7~3.1v, t a =-25 to 85 c) 1. the limitation in continuous write operation is up to 50 times. if you want to write continuously over 50 times, please refer to the technical note. parameter list symbol speed bins units 85ns 1) min max read read cycle time t rc 85 - ns address access time t aa - 85 ns chip select to output t co - 85 ns output enable to valid output t oe - 40 ns ub , lb access time t ba - 85 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 5 - ns write write cycle time t wc 85 - ns chip select to end of write t cw 70 - ns address set-up time t as 0 - ns address valid to end of write t aw 70 - ns ub , lb valid to end of write t bw 70 - ns write pulse width t wp 60 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 25 ns data to write time overlap t dw 35 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns
kab0xd100m - txgp revision 1.11 august 2003 - 66 - mcp memory sec only address data out previous data valid data valid u t ram timing diagrams timing waveform of read cycle(1) (address controlled , cs u = oe =v il , zz = we= v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( zz = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. the minimum read cycle( t rc ) is determined later one of the t rc1 and t rc2. 4. t oe (max) is met only when oe becomes enable after t aa (max). data valid high-z t rc1 t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t rc2 t co address cs u ub , lb oe data out
kab0xd100m - txgp revision 1.11 august 2003 - 67 - mcp memory sec only t as(3) timing waveform of write cycle(1) ( we controlled , zz =v ih ) timing waveform of write cycle(2) ( cs u controlled , zz =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs u address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs u t wr(4)
kab0xd100m - txgp revision 1.11 august 2003 - 68 - mcp memory sec only timing waveform of write cycle(3) ( ub , lb controlled , zz =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs u and low we . a write begins when cs u goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs u goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs u going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs u or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs u timing waveform of deep power down mode (deep power down mode) 1. when you toggle zz pin low, the device gets into the deep power down mode after 0.5 m s suspend period. 2. to return to normal operation, the device needs wake up period. 3. wake up sequence is just the same as power up sequences. zz mode deep power down mode normal operation 0.5 m s 200 m s normal operation read operation twice or stay high during 300 m s suspend wake up cs u ? ?
kab0xd100m - txgp revision 1.11 august 2003 - 69 - mcp memory sec only timing waveform of power up(1) (power up(1)) 1. after vcc u reaches vcc u (min.) following power application, wait 200 m s with cs u high and then toggle cs u low and commit read oper- ation at least twice. then you get into the normal operation. 2. read operation should be executed by toggling cs u pin low. 3. the read operation must satisfy the specified trc. 4. zz pin should be kept high during whole power up sequence. (power up(2)) 1. after vcc u reaches vcc u (min.) following power application, wait 200 m s and wait another 300 m s with cs u high if you don?t want to com- mit dummy read cycle. after total 500 m s wait, toggle cs u low, then you get into the normal mode. 2. zz pin should be kept high during whole power up sequence. 200 m s read operation twice vcc u zz cs u ? vcc u (min) 200 m s vcc u zz cs u 300 m s ? ? vcc u (min) timing waveform of power up(2) (no dummy cycle)
kab0xd100m - txgp revision 1.11 august 2003 - 70 - mcp memory sec only technical note u t ram usage and timing introduction u t ram is based on single-transistor dram cells. as with any other dram, the data in these cells must be periodically refreshed to prevent data loss. what makes the u t ram unique is that it offers a true sram style interface that hides all refresh operations from the memory controller. start with a dram technology the key point of u t ram is its high speed and low power. this high speed comes from the use of many small blocks such as 32kbits each to create u t ram arrays. the small blocks have short word lines thus with little capacitance eliminating a major factor of operating current dissipation in conventional dram blocks. each independent macro-cell on a u t ram device consists of a number of these blocks. each chip has one or more macro. the address decoding logic is also fast. u t ram performs a complete read operation in every trc, but u t ram needs power up sequence like dram. power up sequence and diagram 1. apply power. 2. maintain stable power for a minium 200 m s with cs u =high. 3. issue read operation at least 2 times. design achieves sram specific operations the u t ram was designed to work just like an sram - without any waits or other overhead for precharging or refreshing its internal dram cells. samsung electronics(samsung) hides these operations inside with advanced design technology - those are not to be seen from outside. precharging takes place during every access, overlapped between the end of the cycle and the decoding portion of the next cycle. hiding refresh is more difficult. every row in every block must be refreshed at least once during the refresh interval to prevent data loss. samsung provides an internal refresh controller for devices. when all accesses within refresh interval are directed to one macro-cell, as can happen in signal processing applica- tions, a more sophisticated approach is required to hide refresh. the pseudo sram is sometimes used on these appli- cations, which requires a memory controller that can hold off accesses when a refresh operation is needed. samsung?s unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power con- sumption) is that the u t ram never need to hold off accesses, and indeed it has no hold off signal. the circuitry that gives samsung this advantage is fairly simple but has not previ- ously been disclosed. avoid timing following figures show you an abnormal timing which is not supported on u t ram and its solution. if your system has a timing which sustains invalid states over 4 m s at read mode like figure 29, there are some guide lines for proper operation of u t ram. when your system has multiple invalid address signals shorter than trc on the timing shown in figure 1, u t ram needs a nor- mal read timing(trc) during that cycle(figure 30) or needs to toggle cs u once to ?high? for about ?trc?(figure 31). cs u =v il , ub or/and lb =v il zz =v ih read operation(2 times) power on initial state (wait 200 m s) active cs u =v ih cs u we address less than trc over 4 m s cs u we address trc over 4 m s figure 30. put on read operation every 4 m s figure 29.
kab0xd100m - txgp revision 1.11 august 2003 - 71 - mcp memory sec only figure 31. cs u we address over 4 m s trc toggle cs u to high every 4 m s cs u we address twp over 4 m s twc write operation has similar restriction to read operation. if your system has a timing which sustains invalid states over 4 m s at write mode and has continuous write signals with length of min. twc over 4 m s like figure 32, you must toggle we once to high figure 33. figure 32. cs u we address twp over 4 m s twc trc figure 34. cs u we address twp over 4 m s twc trc and make it stay high at least for trc every 4 m s or toggle cs u once to high for about trc. toggle cs u to high every 4 m s toggle we to high and make it stay high at least for trc every 4 m s
kab0xd100m - txgp revision 1.11 august 2003 - 72 - mcp memory sec only package dimension 80-ball tape ball grid array package (measured in millimeters) top view bottom view 0.08 max 0 . 4 5 0 . 0 5 0.32 0.05 1.30 0.10 a b c e g d f h 0.80x7=5.60 a 0 . 8 0 x 1 2 = 9 . 6 0 1 2 . 0 0 0 . 1 0 80- ? 0.45 0.05 j 4 . 8 0 0 . 8 0 b 8.00 0.10 0.20 m a b ? (datum a) (datum b) 1 4 2 7 6 5 3 8 2.80 #a1 index mark(optional) l k m n 8.00 0.10 1 2 . 0 0 0 . 1 0 #a1 1 2 . 0 0 0 . 1 0 0 . 8 0 side view

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